Verilog is a hardware description language used to model digital systems. To write Verilog code, you need to understand its syntax, including how comments work, the use of whitespace, operators, and how numbers are represented. This guide will break down these elements in easy-to-understand terms and provide examples to help you get started with Verilog programming.
1. Lexical Conventions in Verilog
Verilog syntax is similar to C in that it uses a stream of tokens. These tokens can be comments, keywords, numbers, strings, or whitespace. Every line in Verilog should end with a semicolon (;). Verilog is case-sensitive, meaning var_a and var_A are treated as different identifiers.
2. Comments in Verilog
In Verilog, comments help document the code, making it easier for others to understand. There are two types of comments:
a) Single-line Comments
A single-line comment begins with // and everything after it, up to the end of the line, is considered a comment.
Example:
// This is a single line comment
integer a; // This is a comment next to a variable declarationb) Multi-line Comments
Multi-line comments start with /* and end with */. These comments can span multiple lines but cannot be nested.
Example:
/*
This is a multi-line comment.
It can span several lines.
*/You can also have single-line comments inside a multi-line comment:
/*
This is a multi-line comment.
// This is a single-line comment inside a multi-line comment
*/3. Whitespace in Verilog
Whitespace includes spaces, tabs, and newlines. While whitespace is typically ignored by Verilog, it is useful for separating tokens in code for better readability. However, spaces and tabs within strings are preserved.
Example:
reg [8*6:1] name = "Hello!"; // The spaces at the beginning are ignored
reg [8*6:1] addr = "Earth "; // Notice the space in the string4. Operators in Verilog
Verilog uses different types of operators, categorized as unary, binary, and ternary operators.
a) Unary Operators
Unary operators act on a single operand.
Example:
x = ~y; // ~ is a unary operator, acting on yb) Binary Operators
Binary operators require two operands, one on each side of the operator.
Example:
x = y | z; // | is a binary operator, acting on y and zc) Ternary (Conditional) Operators
The ternary operator is used for conditional operations and involves three operands.
Example:
x = (y > 5) ? w : z; // If y > 5, x gets the value of w, otherwise x gets z5. Number Formats in Verilog
In Verilog, numbers can be expressed in different formats: decimal, binary, octal, and hexadecimal. By default, Verilog treats numbers as decimal.
Examples:
- Decimal:
16(represents 16 in decimal) - Hexadecimal:
0x10(represents 16 in hexadecimal) - Binary:
10000(represents 16 in binary) - Octal:
20(represents 16 in octal)
6. Sized and Unsized Numbers
a) Sized Numbers
Sized numbers specify the number of bits for a given value. The syntax is:
[size]'[base_format][number]sizeis the number of bits.base_formatcan bebfor binary,dfor decimal,hfor hexadecimal, andofor octal.numberis the actual value in the specified base.
Examples:
3'b010; // 3-bit binary value (010, which is 2 in binary)
3'd2; // 3-bit decimal value (2 in decimal)
8'h70; // 8-bit hexadecimal value (70 in hex = 112 in decimal)
9'h1FA; // 9-bit hexadecimal value (1FA in hex = 506 in decimal)b) Unsized Numbers
If no size is specified, the number is assumed to have a default bit-width, based on the system’s settings.
integer a = 5423; // Decimal value of 5423
integer a = 'h1AD7; // 32-bit hexadecimal value 0x1AD7c) Negative Numbers
To represent negative numbers, use a minus sign (-) before the size. It’s important to note that placing the minus sign between the base format and the number is illegal.
Example:
-6'd3; // 6-bit negative decimal number (two's complement of 3)
-6'sd9; // 6-bit signed decimal value of -97. Strings in Verilog
In Verilog, a string is a sequence of characters enclosed in double quotes (" "). A string cannot span multiple lines and each character occupies one byte.
Examples:
"Hello World!"; // A string with 12 characters, requiring 12 bytes
"x + z"; // A string with 5 charactersAttempting to split a string across multiple lines is illegal:
"Hello
World!"; // This is illegal8. Identifiers in Verilog
Identifiers are names given to variables, functions, and modules in Verilog. These names must consist of letters (a-z, A-Z), numbers (0-9), underscores (_), or dollar signs ($). Identifiers cannot start with a digit or a dollar sign.
Valid Identifiers:
integer var_a; // Valid: uses letters and underscore
integer v$ar_a; // Valid: uses letters and dollar signInvalid Identifiers:
integer $var_a; // Invalid: starts with a dollar sign
integer 2var; // Invalid: starts with a digit9. Keywords in Verilog
Keywords in Verilog are reserved words that have special meanings and cannot be used as identifiers. They are written in lowercase letters.
Example keywords include:
moduleinputoutputregwire
10. Verilog Revisions
Verilog has gone through several revisions, with key changes made between 1995 and 2001. These revisions introduced new features and improvements to the language.
11. Summary Table: Common Verilog Syntax Elements
| Element | Description | Example |
|---|---|---|
| Comments | Use // for single-line or /* */ for multi-line. | // This is a comment |
| Whitespace | Spaces, tabs, and newlines are ignored unless in strings. | reg [8*6:1] name = "Hello!"; |
| Operators | Unary (~), Binary (|), Ternary (?:) | x = ~y;, x = y | z;, x = (y > 5) ? w : z; |
| Sized Numbers | Specify bit width and base format. | 3'b010, 8'h70, 32'd100 |
| Strings | Sequence of characters enclosed in double quotes. | "Hello World!" |
| Identifiers | Names of variables, must follow specific rules. | integer var_a; |
| Keywords | Reserved words with special meanings. | module, input, output |
With this detailed guide, you should have a better understanding of Verilog syntax. Whether you’re starting out or brushing up on your Verilog knowledge, understanding comments, operators, and number formats is essential to writing clean and functional code.
