In Verilog, net strengths refers to the ability of a driver to influence the value of a net. It helps simulate real-world behavior in digital circuits by specifying how strongly a driver can affect the state of a net. There are two main types of strength in Verilog: Charge Strengths and Drive Strength. This article explains both in detail, along with the commonly used Verilog strength keywords and examples.

Type of Strengths in Verilog

Charge Strength

Charge strength is used with trireg nets to model charge storage. It indicates the size of the capacitance connected to a net. This strength controls how quickly the charge can decay on a net when it isn’t actively driven. It is essential for simulating capacitive behavior in circuits.

• Small, Medium, and Large charge strengths represent the size of the charge storage.
• Default Charge Strength: The default charge strength for a trireg net is medium.
• Charge Decay Time: The time it takes for the charge to decay is specified when using the delay specification.

Example:

trireg a_net;                     // Medium charge strength by default
trireg (medium) #(0, 0, 100) cap1;  // Medium charge strength, decay time of 100 units
trireg (large) [3:0] cap2;         // Large charge strength, no decay time

Drive Strength

Drive strength refers to the ability of a driver to set the value of a net. It defines how strongly a signal is driven by the output of a gate or net. This strength becomes crucial when multiple drivers are influencing the same net.

• Default Drive Strength: By default, strong drive strength is used.
• Resolving Conflicts: When multiple drivers are trying to control a net, the net adopts the value from the strongest driver. If two drivers with the same strength provide conflicting values, the result is unknown (x).

Example:

assign (strong1, weak0) out = a & b;  // Drives 'out' with strong1 if a & b evaluates to 1

In this example, the output out will be driven strongly when the expression a & b is 1. If it’s 0, the signal is driven weakly.

Verilog Strengths Keywords

Verilog provides several keywords to define different types of net strength. These include:

Practical Examples of Verilog Strengths

Let’s break down some Verilog strength assignments with real-world examples.

Supply Nets

• supply0: Always low (0).
• supply1: Always high (1).

These are typically used to model power connections (ground or Vcc).

assign supply0_net = supply0; // Always drives low
assign supply1_net = supply1; // Always drives high

Strong Drivers

• strong0: Strongly drives the net to logic low (0).
• strong1: Strongly drives the net to logic high (1).

When you want to make sure that a net has a defined value (either low or high) regardless of other drivers, you use strong drivers.

assign (strong1, weak0) strong1_net = a;  // Strong drive to high
assign (strong0, weak1) strong0_net = b;  // Strong drive to low

Pull Drivers

• pull0: Pull-down to 0 when no active drivers are present.
• pull1: Pull-up to 1 when no active drivers are present.

assign (pull1, pull0) pull1_net = c;  // Pull-up to 1 unless driven low
assign (pull0, pull1) pull0_net = d;  // Pull-down to 0 unless driven high

Weak Drivers

• weak0: Weakly drives the net to low (0).
• weak1: Weakly drives the net to high (1).

These allow for weaker drivers but still provide a defined value if no stronger driver is present.

assign (weak1, weak0) weak1_net = a;  // Weak drive to high if 'a' is 1
assign (weak0, weak1) weak0_net = b;  // Weak drive to low if 'b' is 0

High-Impedance Drivers

• highz0: High-impedance state, driven to low (0) when no driver is active.
• highz1: High-impedance state, driven to high (1) when no driver is active.

assign (highz1, pull0) highz1_net = a; // High impedance when not driven
assign (highz0, pull1) highz0_net = b; // High impedance when not driven

Verilog Simulation Example

Here’s a simple Verilog testbench with various strength assignments:

module tb;

    // Declare nets
    reg a, b, c, d;
    wire strong0_net, strong1_net;
    wire pull0_net, pull1_net;
    wire weak0_net, weak1_net;
    wire highz0_net, highz1_net;

    // Assign strong drivers
    assign (strong1, weak0) strong1_net = a;
    assign (weak1, strong0) strong0_net = b;

    // Assign pull drivers
    assign (pull1, pull0) pull1_net = c;
    assign (pull0, pull1) pull0_net = d;

    // Assign weak drivers
    assign (weak1, weak0) weak1_net = a;
    assign (weak0, weak1) weak0_net = b;

    // Assign high impedance drivers
    assign (highz1, pull0) highz1_net = a;
    assign (highz0, pull1) highz0_net = b;

    initial begin
        reg [1:0] values = {1'b1, 1'b0};
        repeat (10) begin
            integer idx;
            #10;
            idx = $random % 2; a = values[idx];
            idx = $random % 2; b = values[idx];
            idx = $random % 2; c = values[idx];
            idx = $random % 2; d = values[idx];
        end
    end

    initial
        $monitor("[%0t] a=%0b b=%0b c=%0b d=%0b strong1=%0b strong0=%0b pull1=%0b pull0=%0b weak1=%0b weak0=%0b highz1=%0b highz0=%0b", $time, a, b, c, d, strong1_net, strong0_net, pull1_net, pull0_net, weak1_net, weak0_net, highz1_net, highz0_net);

endmodule

Simulation Output:

[0] a=x b=x c=x d=x strong1=x strong0=x pull1=x pull0=x weak1=x weak0=x highz1=x highz0=x
[10] a=0 b=x c=x d=x strong1=0 strong0=x pull1=x pull0=x weak1=0 weak0=x highz1=0 highz0=x
...

Conclusion

Verilog strengths are essential for defining how drivers affect nets in a simulation, ensuring that digital circuits behave realistically. By understanding the various types of strength—charge strength and drive strength—along with the common keywords, you can create more accurate and reliable Verilog models. Always ensure to use the correct driver strength in your designs to avoid conflicts and unexpected behavior.