Verilog operators play a crucial role in digital circuits and computer systems by enabling efficient data processing. it provides a wide range of operators that assist synthesis tools in generating the necessary hardware components. These operators include vector operations for arithmetic, relational, equality, logical, bitwise, and shift operations, helping to optimize circuit design and functionality.

Let’s dive into the different types of operators

Verilog Arithmetic Operator

Verilog’s arithmetic operators perform basic mathematical operations like addition, subtraction, multiplication, division, modulo, and exponentiation. It’s important to note:

  • If the second operand of division or modulus is zero, the result is X.
  • If either operand of the power operator is a real number, the result is real.
  • The result of the power operator is 1 if the second operand is 0.

List of Arithmetic Operators

OperatorDescription
a + ba plus b
a - ba minus b
a * ba multiplied by b
a / ba divided by b
a % ba modulo b
a ** ba to the power of b

Example Code of Verilog Operators

module verilog_operators;
  reg [7:0] data1;
  reg [7:0] data2;

  initial begin
    data1 = 45;
    data2 = 9;

    $display ("Add + = %d", data1 + data2);
    $display ("Sub - = %d", data1 - data2);
    $display ("Mul * = %d", data1 * data2);
    $display ("Div / = %d", data1 / data2);
    $display ("Mod %% = %d", data1 % data2);
    $display ("Pow ** = %d", data2 ** 2);
  end
endmodule

Verilog Relational Operators

Relational operators compare two values and return 1 if the condition is true, and 0 if false. If either operand is X or Z, the result is X.

List of Relational Operators

OperatorDescription
a < ba less than b
a > ba greater than b
a <= ba less than or equal to b
a >= ba greater than or equal to b

Example Code of Relational Operators

module relational_example;
  reg [7:0] data1;
  reg [7:0] data2;

  initial begin
    data1 = 45;
    data2 = 9;

    $display ("Result for data1 >= data2: %0d", data1 >= data2);
    data1 = 45; data2 = 45;
    $display ("Result for data1 <= data2: %0d", data1 <= data2);
    data1 = 9;  data2 = 8;
    $display ("Result for data1 > data2: %0d", data1 > data2);
    data1 = 22; data2 = 22;
    $display ("Result for data1 < data2: %0d", data1 < data2);
  end
endmodule

Verilog Equality Operators

Equality operators in Verilog compare two values and return 1 if the values are equal (or not equal) and 0 if they aren’t. These operators also handle X and Z values.

List of Equality Operators

OperatorDescription
a === ba equal to b (including X and Z)
a !== ba not equal to b (including X and Z)
a == ba equal to b (can be unknown)
a != ba not equal to b (can be unknown)

Example Code of Equality Operators

module equality_example;
  reg [7:0] data1;
  reg [7:0] data2;

  initial begin
    data1 = 45;     data2 = 9;
    $display ("data1 === data2: %0d", data1 === data2);
    data1 = 'b101x; data2 = 'b1011;
    $display ("data1 === data2: %0d", data1 === data2);
    data1 = 39;     data2 = 39;
    $display ("data1 == data2: %0d", data1 == data2);
  end
endmodule

Verilog Logical Operators

Logical operators are used to perform logical operations like AND, OR, and NOT on boolean values.

List of Logical Operators

OperatorDescription
a && bLogical AND, evaluates to true if both are true
a || bLogical OR, evaluates to true if either is true
!aLogical NOT, converts non-zero to 0 and zero to 1

Example Code Logical Operators

module logical_example;
  reg [7:0] data1;
  reg [7:0] data2;

  initial begin
    data1 = 45;     data2 = 9;
    $display ("data1 && data2: %0d", data1 && data2);
    data1 = 0;      data2 = 4;
    $display ("data1 && data2: %0d", data1 && data2);
    data1 = 4; 
    $display ("!data1: %0d", !data1);
  end
endmodule

Verilog Bitwise Operators

Bitwise operators perform operations on individual bits of two operands. The result is computed for each bit pair.

List of Bitwise Operators

OperatorDescription
&Bitwise AND
|Bitwise OR

Example Code of Bitwise Operators

module bitwise_example;
  reg [3:0] data1;
  reg [3:0] data2;

  initial begin
    data1 = 4'b1010; data2 = 4'b1100;
    $display ("data1 & data2 = %b", data1 & data2);
    $display ("data1 | data2 = %b", data1 | data2);
  end
endmodule

Verilog Shift Operators

Shift operators move bits left or right in a binary number. There are two types:

  • Logical Shift: << (left), >> (right)
  • Arithmetic Shift: <<< (left), >>> (right)

Example Code Shift Operators

module shift_example;
  reg [7:0] data;
  int i;

  initial begin
    data = 8'b00000001;
    $display ("Original data = %b", data);
    for (i = 0; i < 8; i++) begin
      $display ("data << %0d = %b", i, data << i);
    end
    for (i = 0; i < 8; i++) begin
      $display ("data >> %0d = %b", i, data >> i);
    end
  end
endmodule

Simulation Log

Original data = 00000001
data << 0 = 00000001
data << 1 = 00000010
data << 2 = 00000100
data << 3 = 00001000
data << 4 = 00010000
data << 5 = 00100000
data << 6 = 01000000
data << 7 = 10000000
data >> 0 = 00000001
data >> 1 = 00000000

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