In Verilog, net types represent physical connections between different components in digital circuits. These nets don’t store values themselves. Instead, their value is determined by the components (drivers) connected to them. If no driver is connected, the net typically assumes a default value of ‘z’ (high impedance).

Common Verilog Net Types

Verilog provides several net types, each serving different purposes in modeling digital circuits. Here’s a list of the most commonly used net types:

Types of Nets in Verilog

1. Wire and Tri Nets

Wire nets and tri nets are both used to represent connections in digital circuits. Though they have the same syntax, they differ in purpose:

• Wire Nets:
• Used for connections driven by a single source.
• Ideal for circuits where one gate or one continuous assignment controls the net.
• Tri (Tristate) Nets:
• Used for nets with multiple drivers, often in bus systems where different components can drive the net at different times.
• “Tri” suggests the possibility of a third state, high impedance (‘z’), allowing multiple components to share a connection without interference.

When multiple drivers with conflicting values attempt to drive a wire or tri net, the result is an unknown (x) value.

2. Wired Nets: Wired OR and AND Configurations

Verilog provides special nets to model wired logic, such as wired OR (wor) and wired AND (wand). These nets allow for more complex behavior when multiple drivers are involved.

Other wired nets like trior and triand support multiple drivers but with the same OR and AND behavior respectively.

Here’s an example simulation comparing the wired nets to a standard wire:

module tb;
  wor      wor_net;
  wand     wand_net;
  trior    trior_net;
  triand   triand_net;

  wire     normal_net;

  reg      driver_1;
  reg      driver_2;
  reg [3:0] values;

  assign wor_net = driver_1;
  assign wor_net = driver_2;

  assign trior_net = driver_1;
  assign trior_net = driver_2;

  assign wand_net = driver_1;
  assign wand_net = driver_2;

  assign triand_net = driver_1;
  assign triand_net = driver_2;

  assign normal_net = driver_1;
  assign normal_net = driver_2;

  initial
    $monitor("[%0t] driver_1=%0b driver_2=%0b normal=%0b wor=%0b wand=%0b trior=%0b triand=%0b", $time, driver_1, driver_2, normal_net, wor_net, wand_net, trior_net, triand_net);

  initial begin
    values = {1'bZ, 1'bX, 1'b1, 1'b0};

    for (integer i = 0; i < 4; i++) begin
      for (integer j = 0; j < 4; j++) begin
        driver_1 = values[i];
        driver_2 = values[j];
        #10;
      end
    end
  end
endmodule

Simulation Log:

3. Trireg Net

The trireg net is special because it can store a value. Unlike regular nets, trireg holds its last driven value when no active drivers are present. This makes it useful for modeling storage elements like capacitors.

• Driven State: When any driver is active, the trireg takes the value from that driver.
• Capacitive State: When all drivers are in high-impedance state (z), the trireg retains its last driven value.

4. Tri0 and Tri1 Nets

tri0 and tri1 are specialized nets that model resistive pull-up and pull-down devices. They are used when you want to enforce specific default values when no driver is connected.

• Tri0: Represents a wire with a resistive pull-down device. If no driver is present, the net is 0.
• Tri1: Represents a wire with a resistive pull-up device. If no driver is present, the net is 1.

Here’s an example of how to simulate these nets:

module tb;
  tri0    tri0_net;
  tri1    tri1_net;

  wire    normal_net;

  reg     driver_1;
  reg     driver_2;
  reg [3:0] values;

  assign tri0_net = driver_1;
  assign tri0_net = driver_2;

  assign tri1_net = driver_1;
  assign tri1_net = driver_2;

  assign normal_net = driver_1;
  assign normal_net = driver_2;

  initial
    $monitor("[%0t] driver_1=%0b driver_2=%0b normal=%0b tri0=%0b tri1=%0b", $time, driver_1, driver_2, normal_net, tri0_net, tri1_net);

  initial begin
    values = {1'bZ, 1'bX, 1'b1, 1'b0};

    for (integer i = 0; i < 4; i++) begin
      for (integer j = 0; j < 4; j++) begin
        driver_1 = values[i];
        driver_2 = values[j];
        #10;
      end
    end
  end
endmodule

Simulation Log:

5. Unresolved Nets (uwire)

The uwire is used for nets that should have only one driver. If multiple drivers attempt to drive the same uwire, it will result in a compile-time error. This ensures that there is no contention between drivers.

6. Supply Nets

Verilog also includes supply0 and supply1 nets, which are used to model power supplies in a circuit. They represent supply nets with low (supply0) or high (supply1) strength, indicating the level of power available to the components.

Conclusion

Verilog offers several net types that help model different behaviors of digital circuits. From basic connections like wire and tri nets to more advanced configurations like trireg and tri0/tri1, understanding how and when to use these nets is crucial for accurate simulation and hardware design. These net types ensure flexibility and efficiency when designing complex digital systems.