The Verilog if-else-if statement in Verilog is a key conditional structure. It allows the program to choose between different actions based on certain conditions. The statements inside an if block will run only when the given expression evaluates to true (non-zero value). If the condition is false (zero or ‘x’/’z’), the else block, if present, will execute.

This guide will walk you through the syntax, hardware implementation, and provide useful examples for better understanding.

What is an if-else-if Statement?

In Verilog, an if-else-if structure allows the program to make decisions by evaluating conditions one by one. Here’s how it works:

• If the expression evaluates to true (non-zero value), all statements within the if block will execute.
• If the expression is false (i.e., zero, ‘x’, or ‘z’), the program will skip the if block and check the next condition.
• If an else block exists and the expression is false, it will execute instead.

Syntax of if-else-if

Here’s the basic syntax for the if-else-if structure:

if (condition) begin
    // Execute statements if condition is true
end else if (condition2) begin
    // Execute statements if condition2 is true
end else begin
    // Execute statements if no condition is true
end

• if: Executes when the first condition is true.
• else if: Checks another condition if the first one fails.
• else: Executes if all previous conditions are false.

Example Syntax:

if (expression1) begin
    // Execute statement 1
end else if (expression2) begin
    // Execute statement 2
end else begin
    // Execute statement 3
end

Working with if-else in Hardware

if Without else

If an if block doesn’t have an else part, the value remains unchanged for any condition that doesn’t satisfy the expression inside the if.

Example (Without else):

module des (input en, input d, output reg q);

    always @ (en or d)
        if (en)
            q = d;

endmodule

In this example, the output q will be updated when d or en changes. If en is false, q will not be updated.

if with else

When you add an else statement, the behavior becomes more specific, such as updating the output based on clock signals.

Example (With else):

module dff (
    input clk,
    input rstn,
    input d,
    output reg q
);

    always @ (posedge clk) begin
        if (!rstn)
            q <= 0;
        else
            q <= d;
    end

endmodule

This code describes a D flip-flop where q takes the value of d when the clock signal is active. If the reset signal rstn is low, q will be set to 0.

if-else-if Example

Here’s an example where q is incremented or decremented based on the mode input value. The code checks for mode 1 (increment) and mode 2 (decrement). If mode is any other value, no action is taken.

module des (
    input [1:0] mode,
    input clk,
    input rstn,
    output reg [3:0] q
);

    always @ (posedge clk) begin
        if (!rstn)
            q <= 0;
        else begin
            if (mode == 1)
                q <= q + 1;
            else if (mode == 2)
                q <= q - 1;
        end
    end

endmodule

If mode is 1, q will increment, and if mode is 2, q will decrement. For other values of mode, q will remain the same.

Single-bit Mode Example

Here’s the same design as above, but with a 1-bit mode input. The output q will either increment or decrement based on the mode value.

module des (
    input mode,
    input clk,
    input rstn,
    output reg [3:0] q
);

    always @ (posedge clk) begin
        if (!rstn)
            q <= 0;
        else begin
            if (mode)
                q <= q + 1;
            else
                q <= q - 1;
        end
    end

endmodule

In this case, q is updated based on the value of the mode input.

Examples of if-else Statements in Verilog

Example 1: if Without else for Single Statement

module tb;
  int a = 10;

  initial begin
    if (a == 10)
      $display("a is found to be 10");
    $display("Always executed regardless of value of a");
  end
endmodule

Simulation Log:

a is found to be 10
Always executed regardless of value of a

Example 2: if Without else for Multiple Statements

module tb;
  int a = 10;

  initial begin
    if (a == 10) begin
      $display("a is found to be 10");
      $display("It's good to get 10");
    end
    $display("Always executed regardless of value of a");
  end
endmodule

Simulation Log:

a is found to be 10
It's good to get 10
Always executed regardless of value of a

Example 3: if-else for Single Statement

module tb;
  int a = 9;

  initial begin
    if (a == 10)
      $display("a is found to be 10");
    else
      $display("a is NOT 10 :(");
  end
endmodule

Simulation Log:

a is NOT 10 :(

Example 4: if-else for Multiple Statements

module tb;
  int a = 9;

  initial begin
    if (a == 10) begin
      $display("a is found to be 10");
    end else begin
      $display("a is NOT 10 :(");
      $display("Why is a not 10?");
    end
  end
endmodule

Simulation Log:

a is NOT 10 :(
Why is a not 10?

Key Takeaways

• Use if-else statements to control the flow based on conditions in Verilog.
• Enclose multiple statements inside begin and end if needed.
• The else block will execute if the if condition is false.
• In hardware design, these structures are used to control outputs based on inputs and conditions.

Verilog Conditional Syntax Summary

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