The JK flip-flop is a fundamental component in digital electronics. It is one of the most versatile flip-flops used in sequential logic circuits to store one bit of data. The JK flip-flop is often preferred because it eliminates the undefined state found in SR flip-flops, making it more reliable also we will write verilog code for jk flip flop with different types of modeling and type.

In a JK flip-flop, there are four possible states for the inputs:

• Logic 1
• Logic 0
• No Change
• Toggle

This flip-flop is triggered by a clock signal, making it useful for clocked sequential logic circuits.

Key Features of the JK Flip-Flop

• Versatile: Unlike the SR flip-flop, the JK flip-flop does not have an undefined state, making it more stable.
• Clocked Sequential Logic: The JK flip-flop stores one bit of data and changes its state based on the clock signal and input values.
• State Behavior: It has four unique input combinations that determine its state.

Hardware Schematic for JK Flip-Flop

The basic JK flip-flop hardware setup consists of a clock, two inputs (J and K), and one output (Q). Below is a simple Verilog implementation of a basic JK flip-flop.

Verilog Code for Basic JK Flip-Flop

Basic JK Flip-Flop

Here is a basic Verilog code for JK flip-flop that simulates the behavior of the flip-flop using always blocks to trigger on the clock’s positive edge.

module jk_ff (
  input j, 
  input k, 
  input clk, 
  output reg q
);  
   always @ (posedge clk) begin  
      case ({j, k})  
         2'b00 :  q <= q;        // No Change  
         2'b01 :  q <= 0;        // Reset  
         2'b10 :  q <= 1;        // Set  
         2'b11 :  q <= ~q;       // Toggle  
         default : q <= q;      // Default state
      endcase  
   end  
endmodule  

Testbench for JK Flip-Flop

A testbench is required to simulate and test the Verilog code for JK flip-flop. Here is an example testbench:

module tb_jk;  
   reg j, k, clk;  
   wire q;  
   
   // Clock generation
   always #5 clk = ~clk;  
   
   // Instantiate the JK flip-flop
   jk_ff jk0 ( .j(j), .k(k), .clk(clk), .q(q));  
   
   // Test sequence
   initial begin  
      j <= 0;  
      k <= 0;  
      #5 j <= 0; k <= 1;  
      #20 j <= 1; k <= 0;  
      #20 j <= 1; k <= 1;  
      #20 $finish;  
   end  
   
   // Monitor outputs
   initial  
      $monitor("j=%0d k=%0d q=%0d", j, k, q);  
endmodule  

Types of JK Flip-Flops

1. Edge-Triggered JK Flip-Flop

In an edge-triggered JK flip-flop, the state of the flip-flop is determined by the transition of the clock signal (positive edge). It consists of two main parts: a master gated D latch and a slave gated SR latch.

Schematic and Behavior:

• Master latch takes inputs J, K, and clock (C).
• Slave latch takes the outputs of the master latch.
• The clock input controls the master and slave latches to ensure that only one latch is active at a time, eliminating transparency between inputs and outputs.

Verilog Code for Edge-Triggered JK Flip-Flop

module jk_ff_edge_triggered(
  output Q, 
  output Qn, 
  input C, 
  input J, 
  input K, 
  input RESETn
);  
   wire Kn, D, D1, Cn, Cnn, DQ, DQn;  
   
   // Reset logic
   assign D1 = !RESETn ? 0 : D; 
   
   not(Kn, K);  
   and(J1, J, Qn);  
   and(K1, Kn, Q);  
   or(D, J1, K1);  
   not(Cn, C);  
   not(Cnn, Cn);  
   
   // Latch and flip-flop components
   d_latch dl(DQ, DQn, Cn, D1);  
   sr_latch_gated sr(Q, Qn, Cnn, DQ, DQn);  
endmodule  

2. JK Flip-Flop without Reset

A JK flip-flop without reset works similarly to the edge-triggered flip-flop but lacks an external reset feature. Here’s the Verilog implementation:

module jk_ff(clk, j, k, q);
  input clk, j, k;
  output reg q;
  
  always @(posedge clk) begin
    case({j, k})
      2'b00: q <= q;
      2'b01: q <= 0;
      2'b10: q <= 1;
      2'b11: q <= ~q;
      default: q <= q;
    endcase
  end
endmodule

3. JK Flip-Flop with Synchronous Reset

Here is an example of a JK flip-flop with synchronous reset. The flip-flop will reset to 0 when the reset signal is active.

module jk_ff(clk, reset, j, k, q);
  input clk, reset, j, k;
  output reg q;
  
  always @(posedge clk) begin
    if (reset) 
      q <= 0;
    else begin
      case({j, k})
        2'b00: q <= q;
        2'b01: q <= 0;
        2'b10: q <= 1;
        2'b11: q <= ~q;
        default: q <= q;
      endcase
    end
  end
endmodule

4. JK Flip-Flop with Asynchronous Reset

In the case of an asynchronous reset, the flip-flop resets to 0 as soon as the reset signal is active, regardless of the clock.

module jk_ff(clk, reset, j, k, q);
  input clk, reset, j, k;
  output reg q;
  
  always @(posedge clk or negedge reset) begin
    if (~reset)
      q <= 0;
    else begin
      case({j, k})
        2'b00: q <= q;
        2'b01: q <= 0;
        2'b10: q <= 1;
        2'b11: q <= ~q;
        default: q <= q;
      endcase
    end
  end
endmodule

Gate-Level Modeling of JK Flip-Flop

The gate-level modeling of a JK flip-flop uses basic logic gates such as NAND gates to describe the behavior of the flip-flop.

Here’s an example of a JK flip-flop using gate-level modeling:

module jk_ff_gate(q, qbar, clk, j, k);
  input j, k, clk;
  output q, qbar;
  
  wire nand1_out, nand2_out;
  
  // NAND gate logic
  nand(nand1_out, j, clk, qbar);
  nand(nand2_out, k, clk, q);
  nand(q, qbar, nand1_out);
  nand(qbar, q, nand2_out);
endmodule

Behavioral Modeling of JK Flip-Flop

Behavioral modeling is the highest level of abstraction in Verilog. Instead of focusing on gate-level implementation, you describe the flip-flop’s behavior directly, often using a simple truth table.

Truth Table for JK Flip-Flop:

Verilog Code for Behavioral Modeling

module jkff_behave(clk, j, k, q, qbar);
  input clk, j, k;
  output reg q, qbar;
  
  always @(posedge clk) begin
    if (k == 0) begin
      q <= 0;
      qbar <= 1;
    end
    else if (j == 1) begin
      q <= 0;
      qbar <= 0;
    end
    else if (j == 0 & k == 0) begin
      q <= q;
      qbar <= qbar;
    end
    else if (j == 1 & k == 1) begin 
      q <= ~q; 
      qbar <= ~qbar; 
    end 
  end 
endmodule

RTL Schematic of JK Flip Flop

Conclusion

The JK flip-flop is an essential building block in sequential logic circuits. Using Verilog, it can be modeled at various abstraction levels, from gate-level to behavioral modeling. Understanding the Verilog code for JK flip-flop and how it works is fundamental to designing complex digital circuits.