Verilog Code for D Flip Flop: A Simple Guide

A D flip flop is a fundamental digital circuit that stores a single bit of data. It has a data input ‘D‘, a clock input ‘clk‘, and an output ‘Q‘. The D flip flop transfers the value from the ‘D‘ input to the ‘Q‘ output on the clock’s edge, either rising or falling. This makes it an edge-triggered memory element. The output holds its value until the next clock pulse. In this article, we will discuss Verilog code for D Flip Flop, explain how the flop works, and provide examples of rising edge and falling edge , with both synchronous and asynchronous resets.

Table of Contents

D Flip Flop Truth Table

Here is the truth table for the D flip flop:

D (Data Input)	Clock (clk)	Q (Output)
0	Rising Edge	0
1	Rising Edge	1
0	Falling Edge	0
1	Falling Edge	1

Types of D Flip Flops

Rising Edge D Flip Flop: The output updates on the rising edge of the clock.
Falling Edge D Flip Flop: The output updates on the falling edge of the clock.

Verilog Code for D Flip Flop

The Verilog code for a D flip flop can be written using an always block with edge-triggered statements. Below are examples for both rising edge and falling edge flip flops with different reset options.

Verilog Code for Rising Edge D Flip Flop

Basic Rising Edge D Flip Flop

This code describes a simple rising-edge D flip flop. The output Q follows the input D on the rising edge of the clock.

module RisingEdge_DFlipFlop(D, clk, Q);
  input D;    // Data input
  input clk;  // Clock input
  output Q;   // Output

  always @(posedge clk)
  begin
    Q <= D;
  end
endmodule

Rising Edge D Flip Flop with Synchronous Reset

This version adds a synchronous reset. When sync_reset is high, the output Q will be set to 0.

module RisingEdge_DFlipFlop_SyncReset(D, clk, sync_reset, Q);
  input D;          // Data input
  input clk;        // Clock input
  input sync_reset; // Synchronous reset
  output reg Q;     // Output

  always @(posedge clk)
  begin
    if(sync_reset == 1'b1)
      Q <= 1'b0;  // Reset the output
    else
      Q <= D;     // Transfer input D to output Q
  end
endmodule

Rising Edge D Flip Flop with Asynchronous Reset (High Level)

Here, the output Q resets asynchronously when async_reset is high.

module RisingEdge_DFlipFlop_AsyncResetHigh(D, clk, async_reset, Q);
  input D;            // Data input
  input clk;          // Clock input
  input async_reset;  // Asynchronous reset (high level)
  output reg Q;       // Output

  always @(posedge clk or posedge async_reset)
  begin
    if(async_reset == 1'b1)
      Q <= 1'b0;  // Reset the output on high reset
    else
      Q <= D;     // Transfer input D to output Q
  end
endmodule

Rising Edge D Flip Flop with Asynchronous Reset (Low Level)

This version resets the output when async_reset is low.

module RisingEdge_DFlipFlop_AsyncResetLow(D, clk, async_reset, Q);
  input D;             // Data input
  input clk;           // Clock input
  input async_reset;   // Asynchronous reset (low level)
  output reg Q;        // Output

  always @(posedge clk or negedge async_reset)
  begin
    if(async_reset == 1'b0)
      Q <= 1'b0;  // Reset the output on low reset
    else
      Q <= D;     // Transfer input D to output Q
  end
endmodule

Verilog Code for Falling Edge D Flip Flop

Basic Falling Edge D Flip Flop

This code describes a simple falling-edge D flip flop. The output Q follows the input D on the falling edge of the clock.

module FallingEdge_DFlipFlop(D, clk, Q);
  input D;    // Data input
  input clk;  // Clock input
  output reg Q;  // Output

  always @(negedge clk)
  begin
    Q <= D;
  end
endmodule

Falling Edge D Flip Flop with Synchronous Reset

This version includes a synchronous reset. If sync_reset is high, the output Q will be reset to 0.

module FallingEdge_DFlipFlop_SyncReset(D, clk, sync_reset, Q);
  input D;          // Data input
  input clk;        // Clock input
  input sync_reset; // Synchronous reset
  output reg Q;     // Output

  always @(negedge clk)
  begin
    if(sync_reset == 1'b1)
      Q <= 1'b0;  // Reset the output
    else
      Q <= D;     // Transfer input D to output Q
  end
endmodule

Falling Edge D Flip Flop with Asynchronous Reset (High Level)

This version resets the output asynchronously when async_reset is high.

module FallingEdge_DFlipFlop_AsyncResetHigh(D, clk, async_reset, Q);
  input D;            // Data input
  input clk;          // Clock input
  input async_reset;  // Asynchronous reset (high level)
  output reg Q;       // Output

  always @(negedge clk or posedge async_reset)
  begin
    if(async_reset == 1'b1)
      Q <= 1'b0;  // Reset the output
    else
      Q <= D;     // Transfer input D to output Q
  end
endmodule

Falling Edge D Flip Flop with Asynchronous Reset (Low Level)

This version resets the output asynchronously when async_reset is low.

module FallingEdge_DFlipFlop_AsyncResetLow(D, clk, async_reset, Q);
  input D;             // Data input
  input clk;           // Clock input
  input async_reset;   // Asynchronous reset (low level)
  output reg Q;        // Output

  always @(negedge clk or negedge async_reset)
  begin
    if(async_reset == 1'b0)
      Q <= 1'b0;  // Reset the output
    else
      Q <= D;     // Transfer input D to output Q
  end
endmodule

Verilog Testbench to Simulate D Flip Flop

To verify the functionality of the D flip flop, you can use the following testbench code:

`timescale 1ns/1ps;

module tb_DFF();
  reg D;
  reg clk;
  reg reset;
  wire Q;

  // Instantiate the D Flip Flop
  RisingEdge_DFlipFlop_SyncReset dut(D, clk, reset, Q);

  // Generate clock signal
  initial begin
    clk = 0;
    forever #10 clk = ~clk;
  end

  // Stimulate inputs
  initial begin
    reset = 1;
    D = 0;
    #100;
    reset = 0;
    D = 1;
    #100;
    D = 0;
    #100;
    D = 1;
  end
endmodule

Conclusion

This article provides a comprehensive guide to the Verilog code for D flip flop, explaining both rising edge and falling edge flip flops, including variations with synchronous and asynchronous resets. These basic building blocks are essential in digital logic design, used widely in FPGA and ASIC projects.