In Verilog, Blocking vs Non-Blocking assignments are essential concepts that define how variables are updated in a procedural block. Understanding the differences between these two types of assignments is crucial for writing efficient and correct hardware description code. This article explains both types of assignments, provides examples, and demonstrates how they work in simulation.

1. Blocking Assignment in Verilog

What is Blocking Assignment?

In Verilog, a blocking assignment is performed using the = operator. When a variable is assigned using =, the statements are executed sequentially, one after the other, within the same time-step. Blocking assignments will block the execution of the next statement until the current statement is fully completed.

Example of Blocking Assignment

Consider the following Verilog code with blocking assignments:

module tb;
  reg [7:0] a, b, c, d, e;

  initial begin
    a = 8'hDA; // Block 1: Assign a value to 'a'
    $display ("[%0t] a=0x%0h b=0x%0h c=0x%0h", $time, a, b, c);
    b = 8'hF1; // Block 2: Assign a value to 'b'
    $display ("[%0t] a=0x%0h b=0x%0h c=0x%0h", $time, a, b, c);
    c = 8'h30; // Block 3: Assign a value to 'c'
    $display ("[%0t] a=0x%0h b=0x%0h c=0x%0h", $time, a, b, c);
  end

  initial begin
    d = 8'hAA; // Block 4: Assign a value to 'd'
    $display ("[%0t] d=0x%0h e=0x%0h", $time, d, e);
    e = 8'h55; // Block 5: Assign a value to 'e'
    $display ("[%0t] d=0x%0h e=0x%0h", $time, d, e);
  end
endmodule

Simulation Log for Blocking Assignment

The simulation output will look like this:

[0] a=0xda b=0xx c=0xx
[0] a=0xda b=0xf1 c=0xx
[0] a=0xda b=0xf1 c=0x30
[0] d=0xaa e=0xx
[0] d=0xaa e=0x55

Explanation:

• The initial blocks execute in parallel, but each block executes its statements sequentially.
• Blocking assignments update the variables one by one. For example, the first $display shows b and c as 0xXX because their assignments haven’t been executed yet.

Adding Delays to Blocking Assignment

Here is the modified example with delays to see how blocking assignments behave with time delays:

module tb;
  reg [7:0] a, b, c, d, e;

  initial begin
    a = 8'hDA;
    $display ("[%0t] a=0x%0h b=0x%0h c=0x%0h", $time, a, b, c);
    #10 b = 8'hF1;
    $display ("[%0t] a=0x%0h b=0x%0h c=0x%0h", $time, a, b, c);
    c = 8'h30;
    $display ("[%0t] a=0x%0h b=0x%0h c=0x%0h", $time, a, b, c);
  end

  initial begin
    #5 d = 8'hAA;
    $display ("[%0t] d=0x%0h e=0x%0h", $time, d, e);
    #5 e = 8'h55;
    $display ("[%0t] d=0x%0h e=0x%0h", $time, d, e);
  end
endmodule

Simulation Log:

[0] a=0xda b=0xx c=0xx
[5] d=0xaa e=0xx
[10] a=0xda b=0xf1 c=0xx
[10] a=0xda b=0xf1 c=0x30
[10] d=0xaa e=0x55

In this example, delays are used to control when the variables are assigned, allowing us to observe how the blocking assignments behave when time passes.

2. Non-Blocking Assignment in Verilog

What is Non-Blocking Assignment?

A non-blocking assignment uses the <= operator. Unlike blocking assignments, non-blocking assignments allow the execution of subsequent statements without waiting for the current statement to complete. This is especially useful when modeling parallel behavior in hardware.

Example of Non-Blocking Assignment

Here is an example of non-blocking assignments:

module tb;
  reg [7:0] a, b, c, d, e;

  initial begin
    a <= 8'hDA; // Block 1: Assign a value to 'a'
    $display ("[%0t] a=0x%0h b=0x%0h c=0x%0h", $time, a, b, c);
    b <= 8'hF1; // Block 2: Assign a value to 'b'
    $display ("[%0t] a=0x%0h b=0x%0h c=0x%0h", $time, a, b, c);
    c <= 8'h30; // Block 3: Assign a value to 'c'
    $display ("[%0t] a=0x%0h b=0x%0h c=0x%0h", $time, a, b, c);
  end

  initial begin
    d <= 8'hAA; // Block 4: Assign a value to 'd'
    $display ("[%0t] d=0x%0h e=0x%0h", $time, d, e);
    e <= 8'h55; // Block 5: Assign a value to 'e'
    $display ("[%0t] d=0x%0h e=0x%0h", $time, d, e);
  end
endmodule

Simulation Log for Non-Blocking Assignment

The output of the simulation will be:

[0] a=0xx b=0xx c=0xx
[0] a=0xx b=0xx c=0xx
[0] a=0xx b=0xx c=0xx
[0] d=0xx e=0xx
[0] d=0xx e=0xx

Explanation:

• In non-blocking assignments, the right-hand side (RHS) values are captured but not immediately assigned. The left-hand side (LHS) variables receive the captured values only at the end of the time-step.
• As a result, all $display statements show 0xXX for all variables, because they have not yet been updated within the same time-step.

Adding Delays to Non-Blocking Assignment

Here’s the second example with delays added, and non-blocking assignments used:

module tb;
  reg [7:0] a, b, c, d, e;

  initial begin
    a <= 8'hDA;
    $display ("[%0t] a=0x%0h b=0x%0h c=0x%0h", $time, a, b, c);
    #10 b <= 8'hF1;
    $display ("[%0t] a=0x%0h b=0x%0h c=0x%0h", $time, a, b, c);
    c <= 8'h30;
    $display ("[%0t] a=0x%0h b=0x%0h c=0x%0h", $time, a, b, c);
  end

  initial begin
    #5 d <= 8'hAA;
    $display ("[%0t] d=0x%0h e=0x%0h", $time, d, e);
    #5 e <= 8'h55;
    $display ("[%0t] d=0x%0h e=0x%0h", $time, d, e);
  end
endmodule

Simulation Log:

[0] a=0xx b=0xx c=0xx
[5] d=0xx e=0xx
[10] a=0xda b=0xx c=0xx
[10] a=0xda b=0xx c=0x30
[10] d=0xaa e=0

Explanation:

• The variables a, b, c, d, and e are updated only at the end of the time-step, which explains why the first display shows 0xXX.
• The non-blocking assignment allows variables to be scheduled without blocking the execution of other statements.

3. Verilog Blocking vs Non-Blocking Assignments : Comparison

To summarize the key differences between blocking and non-blocking assignments, here’s a comparison table:

Conclusion

Both blocking and non-blocking assignments are powerful tools in Verilog. Blocking assignments are easier to understand and are useful when you want sequential execution. Non-blocking assignments are more suited for modeling hardware where multiple actions occur in parallel. By understanding when and how to use each assignment type, you can write more efficient and accurate Verilog code.