In Verilog, arrays store multiple values in a single variable. You can use arrays for reg, wire, integer, and real data types. Arrays can have one or more dimensions, allowing you to create complex data structures.

Here are some examples of Verilog arrays:

• reg y1 [11:0];
  This creates a 12-element array, where each element is 1-bit wide.
• wire [0:7] y2 [3:0];
  This defines a 4-element array of 8-bit wide wire signals.
• reg [7:0] y3 [0:1][0:3];
  This declares a 2D array with 2 rows and 4 columns, where each element is 8 bits wide.

To access specific elements in an array, you need to provide an index for each dimension. These indexes can also be expressions that involve other variables.

Note: A memory with n 1-bit registers differs from an n-bit wide vector register.

Array Assignment in Verilog

Verilog doesn’t allow you to assign a value to all elements of an array at once. You must assign values to each element individually. Here’s how you assign values to array elements:

y2[0] = 8'ha2;    // Assign 0xA2 to the first element of y2
y2[2] = 8'h1c;    // Assign 0x1C to the third element of y2
y3[1][2] = 8'hdd; // Assign 0xDD to the element at row 1, column 2 of y3
y3[0][0] = 8'haa; // Assign 0xAA to the element at row 0, column 0 of y3

Example of Arrays in Verilog

This code demonstrates how to declare arrays, assign values, and access those values. In this example, mem1 is an 8-bit vector, mem2 is an 8-bit array with a depth of 4, and mem3 is a 16-bit 2D array with 4 rows and 2 columns.

module des ();

  reg [7:0]  mem1;               // 8-bit wide vector
  reg [7:0]  mem2 [0:3];         // 8-bit wide array with depth=4
  reg [15:0] mem3 [0:3][0:1];    // 16-bit wide 2D array with 4 rows and 2 columns

  initial begin
    int i;

    // Assign values to the arrays
    mem1 = 8'ha9;
    $display ("mem1 = 0x%0h", mem1);

    mem2[0] = 8'haa;
    mem2[1] = 8'hbb;
    mem2[2] = 8'hcc;
    mem2[3] = 8'hdd;

    // Display elements of mem2
    for(i = 0; i < 4; i = i+1) begin
      $display("mem2[%0d] = 0x%0h", i, mem2[i]);
    end

    // Assign values to mem3 and display them
    for(i = 0; i < 4; i = i+1) begin
      for(int j = 0; j < 2; j = j+1) begin
        mem3[i][j] = i + j;
        $display("mem3[%0d][%0d] = 0x%0h", i, j, mem3[i][j]);
      end
    end
  end

endmodule

Simulation Output:

mem1 = 0xa9
mem2[0] = 0xaa
mem2[1] = 0xbb
mem2[2] = 0xcc
mem2[3] = 0xdd
mem3[0][0] = 0x0
mem3[0][1] = 0x1
mem3[1][0] = 0x1
mem3[1][1] = 0x2
mem3[2][0] = 0x2
mem3[2][1] = 0x3
mem3[3][0] = 0x3
mem3[3][1] = 0x4

What Are Memories in Verilog?

Memories in Verilog represent digital storage elements, like RAM or ROM, used to store data in digital circuits. In Verilog, you model memory using arrays of reg type variables, where each array element stores a “word” or data unit.

Memories use an address to access specific data, and the value of each array element depends on the address provided.

Register Vectors in Verilog

A register vector stores multiple bits, often representing storage elements like flip-flops or registers. The size of a register vector is determined by the number of bits, and each bit can be accessed individually.

Here’s an example of a Verilog module using a 16-bit register that updates based on control signals:

module des (
    input clk,
    input rstn,
    input wr,
    input sel,
    input [15:0] wdata,
    output [15:0] rdata
);

  reg [15:0] register;

  always @ (posedge clk) begin
    if (!rstn)
      register <= 0;  // Reset the register
    else begin
      if (sel & wr)
        register <= wdata;  // Write data to the register
      else
        register <= register;  // Hold the current value
    end
  end

  assign rdata = (sel & ~wr) ? register : 0;  // Read data from the register

endmodule

Memory Example in Verilog

In this example, register is an array with four 16-bit wide elements. The module uses an input signal called addr to access a specific index of the array.

module des (
    input clk,
    input rstn,
    input [1:0] addr,
    input wr,
    input sel,
    input [15:0] wdata,
    output [15:0] rdata
);

  reg [15:0] register [0:3];  // Array with 4 16-bit registers
  integer i;

  always @ (posedge clk) begin
    if (!rstn) begin
      // Reset all register values to 0
      for (i = 0; i < 4; i = i+1) begin
        register[i] <= 0;
      end
    end else begin
      // Write to register at specified address
      if (sel & wr)
        register[addr] <= wdata;
    end
  end

  assign rdata = (sel & ~wr) ? register[addr] : 0;  // Read from the register at specified address

endmodule

Conclusion

Verilog arrays and memories are powerful tools for modeling and storing data in digital circuits. Arrays help store multiple values in a single variable, while memories store data that can be accessed and modified based on an address. By mastering these concepts, you can write more efficient and organized Verilog code for your designs.

Verilog Array and Memories : Comparison