In SystemVerilog, the super keyword is an essential tool used to access properties and methods from a parent class within a subclass. This guide will explain how to use the systemVerilog super keyword properly and its importance when dealing with inheritance in object-oriented programming.

What Is the “systemVerilog super” Keyword?

The super keyword refers to the immediate base class of a subclass. It allows you to access properties or methods of the base class, especially when they have been overridden by the subclass. Without using the super keyword, you can’t directly access those overridden methods or properties.

How Does the “super” Keyword Work in SystemVerilog?

The super keyword can only be used inside a class scope that inherits from another class (also known as a derived class). When you inherit from a base class, you can use super to call base class methods, even if they are overridden in the child class.

Here’s a simple example of how the systemVerilog super keyword is used:

Example 1: Incorrect Usage of super in SystemVerilog

class Packet;
    int addr;
    
    function display ();
        $display ("[Base] addr=0x%0h", addr);
    endfunction
endclass

class extPacket;  // Missing "extends" keyword
    function new ();
        super.new ();  // Incorrect: 'super' can only be used in a subclass
    endfunction
endclass

module tb;
    Packet p;
    extPacket ep;

    initial begin
        ep = new();  // This will cause an error because extPacket is not a subclass of Packet
        p = new();
        p.display();
    end
endmodule

Simulation Log Output:

ncvlog: *E,CLSSPX (testbench.sv,12|8): 'super' can only be used within a class scope that derives from a base class.

In this example, the code will result in a compilation error because extPacket does not extend the Packet class. The super keyword can only be used within a class that derives from another class, i.e., it must be a subclass.

Correct Usage of the “systemVerilog super” Keyword

Now, let’s look at the correct implementation of the super keyword by ensuring that extPacket properly extends Packet.

class Packet;
    int addr;

    function display ();
        $display ("[Base] addr=0x%0h", addr);
    endfunction
endclass

class extPacket extends Packet;  // extPacket now extends Packet
    function new ();
        super.new ();  // Now this is correct
    endfunction
endclass

module tb;
    Packet p;
    extPacket ep;

    initial begin
        ep = new();
        p = new();
        p.display();
    end
endmodule

Simulation Log Output:

ncsim> run
[Base] addr=0x0
ncsim: *W,RNQUIE: Simulation is complete.

In this case, there are no compilation errors. The super keyword works correctly because extPacket is now a subclass of Packet.

Accessing Base Class Methods Using “systemVerilog super”

The super keyword can also be used to call methods from the base class. Here’s how you can call a method from the base class in a derived class:

class Packet;
    int addr;

    function display ();
        $display ("[Base] addr=0x%0h", addr);
    endfunction
endclass

class extPacket extends Packet;
    function display();
        super.display();  // Calls the display method of the base class
        $display ("[Child] addr=0x%0h", addr);
    endfunction

    function new ();
        super.new ();
    endfunction
endclass

module tb;
    Packet p;
    extPacket ep;

    initial begin
        ep = new();
        p = new();
        ep.display();
    end
endmodule

Simulation Log Output:

ncsim> run
[Base] addr=0x0
[Child] addr=0x0
ncsim: *W,RNQUIE: Simulation is complete.

In this example, the display() function of the base class Packet is called using the super keyword, followed by a custom message from the child class extPacket.

Key Takeaways

• systemVerilog super is used to access methods and properties from the parent class within a subclass.
• You must ensure the subclass extends the parent class for the super keyword to work properly.
• You can use super to invoke methods from the base class, even when they are overridden in the subclass.

Comparison Table: Incorrect vs Correct Use of SystemVerilog Super Keyword

Conclusion

The systemVerilog super keyword is a powerful feature that allows you to interact with the parent class within a subclass. It is essential for maintaining the structure and functionality of object-oriented code in SystemVerilog. By following the correct usage patterns, you can effectively utilize the super keyword to access base class properties and methods in your subclasses.