A SystemVerilog structures allows you to group different data types into one unit. Unlike arrays, where all elements must be of the same data type, structures can store variables of various data types, each referenced by its name. This guide will explore how to define, use, and manipulate structures in SystemVerilog.

What is a SystemVerilog Structures?

A structure in SystemVerilog is a collection of variables, each of potentially different data types, that are grouped together. You can access each element of the structure individually by its name, or refer to the entire structure as a whole.

Here’s the difference between arrays and structures:

Arrays vs. Structures

In the above example, arrays like int arr[10] store elements of the same type, whereas structures allow for more complex data types.

Declaring and Using Structures

Basic Structure Declaration

A structure can be defined using the struct keyword, followed by member declarations inside curly brackets.

Example:

module tb;
    // Create a structure called "st_fruit"
    struct {
        string fruit; // Fruit name
        int count;    // Quantity
        byte expiry;  // Expiry in days
    } st_fruit;

    initial begin
        // Initialize structure variable
        st_fruit = '{"apple", 4, 15};

        // Display the structure variable
        $display ("st_fruit = %p", st_fruit);

        // Change values in the structure
        st_fruit.fruit = "pineapple";
        st_fruit.expiry = 7;
        $display ("st_fruit = %p", st_fruit);
    end
endmodule

Simulation Log:

ncsim> run
st_fruit = '{fruit:"apple", count:4, expiry:'hf}
st_fruit = '{fruit:"pineapple", count:4, expiry:'h7}
ncsim: *W,RNQUIE: Simulation is complete.

In the example above, a structure called st_fruit is created, which holds a fruit name, count, and expiry information. We initialize it, display the values, and modify some fields later.

Creating Multiple Structure Variables with typedef

If you need to create multiple variables of the same structure type, using typedef is a good idea. This defines a custom data type based on the structure.

Example:

module tb;
    // Create a structure called "st_fruit" with typedef
    typedef struct {
        string fruit;
        int count;
        byte expiry;
    } st_fruit;

    initial begin
        // Declare structure variables of type st_fruit
        st_fruit fruit1 = '{"apple", 4, 15};
        st_fruit fruit2;

        // Display the structure variables
        $display ("fruit1 = %p fruit2 = %p", fruit1, fruit2);

        // Assign one structure variable to another and print
        fruit2 = fruit1;
        $display ("fruit1 = %p fruit2 = %p", fruit1, fruit2);

        // Modify fruit1 to see if fruit2 changes
        fruit1.fruit = "orange";
        $display ("fruit1 = %p fruit2 = %p", fruit1, fruit2);
    end
endmodule

Simulation Log:

ncsim> run
fruit1 = '{fruit:"apple", count:4, expiry:'hf} fruit2 = '{fruit:"", count:0, expiry:'h0}
fruit1 = '{fruit:"apple", count:4, expiry:'hf} fruit2 = '{fruit:"apple", count:4, expiry:'hf}
fruit1 = '{fruit:"orange", count:4, expiry:'hf} fruit2 = '{fruit:"apple", count:4, expiry:'hf}
ncsim: *W,RNQUIE: Simulation is complete.

In this example, the typedef allows you to define the structure as a type, making it easier to create multiple variables of the same type.

Packed vs. Unpacked Structures

In SystemVerilog, structures can be packed or unpacked. The default structure is unpacked, meaning it can contain padding between members. Packed structures do not have padding, and their members are tightly packed in memory.

Unpacked Structure

An unpacked structure allows you to define a collection of variables, each with its own memory location, and can be accessed individually.

Packed Structure

A packed structure is stored in memory without gaps, where each field is adjacent to the next, starting from the most significant bit.

Packed Structure Example:

typedef struct packed {
    bit [3:0] mode;   // 4-bit mode
    bit [2:0] cfg;    // 3-bit config
    bit en;           // 1-bit enable
} st_ctrl;

module tb;
    st_ctrl ctrl_reg;

    initial begin
        // Initialize packed structure variable
        ctrl_reg = '{4'ha, 3'h5, 1};
        $display ("ctrl_reg = %p", ctrl_reg);

        // Change packed structure member
        ctrl_reg.mode = 4'h3;
        $display ("ctrl_reg = %p", ctrl_reg);

        // Assign a packed value
        ctrl_reg = 8'hfa;
        $display ("ctrl_reg = %p", ctrl_reg);
    end
endmodule

Simulation Log:

ncsim> run
ctrl_reg = '{mode:'ha, cfg:'h5, en:'h1}
ctrl_reg = '{mode:'h3, cfg:'h5, en:'h1}
ctrl_reg = '{mode:'hf, cfg:'h5, en:'h0}
ncsim: *W,RNQUIE: Simulation is complete.

Explanation:

• mode takes the first 4 bits.
• cfg occupies the next 3 bits.
• en holds the last 1 bit.

When to Use Packed Structures

Packed structures are ideal when you need to work with data where the exact memory layout is important, such as when dealing with hardware registers or communication protocols.

Key Differences Between Packed and Unpacked Structures

Conclusion

Understanding SystemVerilog structures allows you to manage data efficiently in both software and hardware designs. By using packed and unpacked structures, you can tailor your data organization to fit specific needs. Whether you’re creating complex variable groups with different data types or optimizing memory layout for hardware interfacing, structures are a powerful tool in SystemVerilog.

Additional Resources:

• SystemVerilog’s official documentation on structures.
• Tutorials on packed vs unpacked structures for better memory management.

This guide provided you with a detailed overview of SystemVerilog structure, including examples and practical applications. Let me know if you have any further questions or need clarification!