In SystemVerilog, we can declare variables as random using the rand or randc keywords. These random variables can be applied to various data types, including normal variables, arrays, dynamic arrays, and queues. Let’s explore both keywords and how they work.

Using rand for Random Variables

The rand keyword is used to declare standard random variables. These variables generate values uniformly within a specified range. For instance, an 8-bit unsigned integer can hold values between 0 and 255, and any value within this range is equally likely to be assigned when randomized.

Example: Declaring and Randomizing Variables with rand

class Packet;
    rand int       count;
    rand byte      master [$];
    rand bit [7:0] data [];
endclass

In the example above, we define a class Packet with three variables: count, master, and data. These variables are declared as rand, so their values will be randomly generated.

Now, let’s take a simple example where a 3-bit variable named data is randomized 10 times. The function randomize() is called to randomize all rand type variables within the object.

class Packet;
    rand bit [2:0] data;
endclass

module tb;
    initial begin
        Packet pkt = new();
        for (int i = 0; i < 10; i++) begin
            pkt.randomize();
            $display("itr=%0d data=0x%0h", i, pkt.data);
        end
    end
endmodule

Simulation Log Output

When running the above code, the output may look like this:

run -all;
# KERNEL: itr=0 data=0x7
# KERNEL: itr=1 data=0x2
# KERNEL: itr=2 data=0x2
# KERNEL: itr=3 data=0x1
# KERNEL: itr=4 data=0x2
# KERNEL: itr=5 data=0x4
# KERNEL: itr=6 data=0x0
# KERNEL: itr=7 data=0x1
# KERNEL: itr=8 data=0x5
# KERNEL: itr=9 data=0x0
# KERNEL: Simulation has finished. There are no more test vectors to simulate.

In this simulation log, note that some values, such as 0x2 and 0x1, are repeated multiple times. This is because the rand variable allows the same value to appear again due to the uniform distribution over the range.

Understanding randc: Cyclic Randomization

The randc keyword stands for “random-cyclic.” Variables declared with randc cycle through all the possible values within their range before repeating any value. This ensures that each value appears at least once before any value is repeated.

Example: Declaring and Randomizing Variables with randc

class Packet;
    randc int       count;
    randc byte      master [$];
    randc bit [1:0] data [];
endclass

In this case, randc is used to ensure that every value in the range for the data variable (0 to 3) is assigned before any value is repeated.

Example: Randomizing randc Variables

class Packet;
    randc bit [2:0] data;
endclass

module tb;
    initial begin
        Packet pkt = new();
        for (int i = 0; i < 10; i++) begin
            pkt.randomize();
            $display("itr=%0d data=0x%0h", i, pkt.data);
        end
    end
endmodule

Simulation Log Output for randc

When running this simulation, the output may look like this:

run -all;
# KERNEL: itr=0 data=0x6
# KERNEL: itr=1 data=0x3
# KERNEL: itr=2 data=0x4
# KERNEL: itr=3 data=0x7
# KERNEL: itr=4 data=0x0
# KERNEL: itr=5 data=0x1
# KERNEL: itr=6 data=0x5
# KERNEL: itr=7 data=0x2
# KERNEL: itr=8 data=0x5              // Start of a new sequence
# KERNEL: itr=9 data=0x0
# KERNEL: Simulation has finished. There are no more test vectors to simulate.

Here, the randc variable data exhausts all the values in its range (0 to 7) before repeating any value. Notice that after the 7th iteration, the sequence starts repeating from 0x5 again, marking the beginning of a new cycle.

Key Differences Between rand and randc

Conclusion

SystemVerilog provides powerful features for working with random values, especially the rand and randc keywords. The rand keyword generates values randomly and uniformly, whereas randc ensures that all values are used before repeating. These features are essential for simulating and testing a variety of scenarios in hardware design.