In some situations, you may want the SystemVerilog solver to randomly select one statement out of many. The randcase keyword helps in such cases by choosing one of its branches based on assigned weights. Each case in the randcase block has a weight, which determines the probability of that case being selected. The higher the weight, the higher the probability of being chosen.

Syntax of randcase

The syntax for using randcase is simple and works like this:

randcase
    item : statement;
    ...
endcase

How It Works

Each case in a randcase block is assigned a weight. The probability of selecting a branch is determined by dividing the weight of that branch by the total sum of all weights.

For example, consider the following:

• Weight 1: 1/9 or 11.11%
• Weight 2: 5/9 or 55.56%
• Weight 3: 3/9 or 33.33%

These weights show the probability of selecting a specific branch. The higher the weight, the more often that case will be chosen.

Example 1: Using randcase with Weights

Let’s look at an example that demonstrates how randcase works.

module tb;
    initial begin
        for (int i = 0; i < 10; i++) 
            randcase
                1  :  $display("Wt 1");
                5  :  $display("Wt 5");
                3  :  $display("Wt 3");
            endcase
    end
endmodule

Simulation Log:

Wt 5
Wt 5
Wt 3
Wt 5
Wt 1
Wt 3
Wt 5
Wt 3
Wt 3
Wt 5

In this example, Wt 5 is selected most often, while Wt 1 is chosen least often.

Example 2: Disabling Branches with Zero Weight

If you assign a zero weight to a branch in a randcase, that branch will never be selected. Let’s see this in action:

module tb;
    initial begin
        for (int i = 0; i < 10; i++) 
            randcase
                0  :  $display("Wt 1");
                5  :  $display("Wt 5");
                3  :  $display("Wt 3");
            endcase
    end
endmodule

Simulation Log:

Wt 5
Wt 5
Wt 3
Wt 5
Wt 5
Wt 3
Wt 5
Wt 3
Wt 3
Wt 5

Here, the first branch (Wt 1) with zero weight was never chosen.

Example 3: All Branches Have Zero Weight

What happens if all branches have zero weight? In this case, no branch is selected, and a runtime warning will be generated.

module tb;
    initial begin
        for (int i = 0; i < 10; i++) 
            randcase
                0  :  $display("Wt 1");
                0  :  $display("Wt 5");
                0  :  $display("Wt 3");
            endcase
    end
endmodule

Simulation Log:

ncsim: *W,RANDNOB: The sum of the weight expressions in the randcase statement is 0.
No randcase branch was taken.

How the randcase Keyword Works Internally

Each time the randcase is called, the solver generates a random number between 0 and the total sum of all the weights. The cases are selected based on the generated number:

• Smaller random numbers match the first (top) weight statements.
• Larger random numbers match the later statements.

Conclusion

The randcase keyword is an effective way to introduce randomness into your SystemVerilog code, allowing you to control the probability of selecting different branches using weighted values.

Changes and Additional Information

1. Comparison of Weights:

2. No Randomization with Zero Weight:
   • If all the weights are zero, the simulation will not take any branch, resulting in no output.

By following these explanations and examples, you can now easily use randcase to add randomness to your SystemVerilog designs.