https://www.doulos.com/knowhow/systemverilog/systemverilog-tutorials/systemverilog-rtl-tutorial/In SystemVerilog, there are specific constructs used to check for violations in if
–else
statements. These constructs help to identify issues when the conditions don’t match as expected. The key constructs introduced for these checks are:
- unique-if
- unique0-if
- priority-if
Each of these constructs behaves differently and helps in catching violations based on the conditions evaluated in the if
–else
blocks.
What Does Unique-If Do?
The unique-if
construct evaluates conditions in any order and checks for violations based on the following rules:
- Error when no conditions match: If none of the
if
conditions match and there’s no explicitelse
clause, an error is reported. - Error when more than one condition matches: If multiple conditions match, it reports a violation.
Example: Using Unique-If to Check for Violations
Consider the following example where unique-if
is used in an if
–else
construct:
module tb;
int x = 4;
initial begin
// This "unique" construct checks if conditions are met
// No error is reported because there is an "else" clause
unique if (x == 3)
$display("x is %0d", x);
else if (x == 5)
$display("x is %0d", x);
else
$display("x is neither 3 nor 5");
// Error is reported here as no conditions match and there is no "else"
unique if (x == 3)
$display("x is %0d", x);
else if (x == 5)
$display("x is %0d", x);
end
endmodule
Simulation Log:
ncsim> run
x is neither 3 nor 5
ncsim: *W,NOCOND: Unique if violation: Every if clause was false.
File: ./testbench.sv, line = 18, pos = 13
What Does Unique0-If Do?
Unlike unique-if
, the unique0-if
construct does not report a violation if none of the conditions match. It only reports an error if there is more than one match, just like unique-if
. However, it ignores the scenario where no conditions match, making it slightly more lenient than unique-if
.
Using Unique-If with Multiple Conditions
When multiple conditions match, the unique-if
construct reports a violation. Here’s an example where the value of x
matches multiple conditions:
module tb;
int x = 4;
initial begin
// When multiple "if" blocks match, an error is reported
unique if (x == 4)
$display("1. x is %0d", x);
else if (x == 4)
$display("2. x is %0d", x);
else
$display("x is not 4");
end
endmodule
Simulation Log:
ncsim> run
1. x is 4
ncsim: *W,MCONDE: Unique if violation: Multiple true if clauses at {line=8:pos=15 and line=10:pos=13}.
File: ./testbench.sv, line = 8, pos = 15
What Does Priority-If Do?
The priority-if
construct evaluates conditions sequentially. It reports a violation in the following cases:
- No condition is true: If none of the
if
conditions are true and there’s noelse
clause, an error is reported. - No
else
clause: If no conditions match and there’s noelse
clause, a violation is reported.
Example: Using Priority-If for Sequential Evaluation
Here’s an example that shows how priority-if
works when evaluating conditions sequentially:
module tb;
int x = 4;
initial begin
// This "priority" construct checks conditions in sequence
// No error is reported because there is an "else" clause
priority if (x == 3)
$display("x is %0d", x);
else if (x == 5)
$display("x is %0d", x);
else
$display("x is neither 3 nor 5");
// Error is reported here since no conditions match and there's no "else"
priority if (x == 3)
$display("x is %0d", x);
else if (x == 5)
$display("x is %0d", x);
end
endmodule
Simulation Log:
ncsim> run
x is neither 3 nor 5
ncsim: *W,NOCOND: Priority if violation: Every if clause was false.
File: ./testbench.sv, line = 18, pos = 15
Using Priority-If to Exit Early
The priority-if
construct stops evaluating further conditions once a match is found. Here is an example showing this behavior:
module tb;
int x = 4;
initial begin
// Exits early after the first matching condition
priority if (x == 4)
$display("x is %0d", x);
else if (x != 5)
$display("x is %0d", x);
end
endmodule
Simulation Log:
ncsim> run
x is 4
ncsim: *W,RNQUIE: Simulation is complete.
Key Differences Between Unique-If and Priority-If
To summarize, here’s a comparison table highlighting the main differences between unique-if
and priority-if
:
Feature | Unique-If | Priority-If |
---|---|---|
Error when no condition matches | Reports an error if no conditions match and no else clause is present. | Reports an error if no conditions match and no else clause is present. |
Error when multiple conditions match | Reports an error if more than one condition matches. | Does not check for multiple conditions matching. |
Evaluation Order | Evaluates conditions in any order. | Evaluates conditions sequentially. |
Conclusion
In SystemVerilog, both unique-if
and priority-if
constructs are useful for detecting violations in if
–else
statements, but they behave differently. The unique-if
construct checks for violations when no condition matches or when multiple conditions match, while priority-if
evaluates conditions sequentially and reports violations when no condition matches or if there’s no else
clause.
By using these constructs correctly, you can ensure that your code is both functional and free of logical errors, improving overall reliability and performance.