In SystemVerilog, loops allow you to repeatedly execute a block of code based on a given condition. There are several types of loops, each with unique functionality. This article will explain the most commonly used loop types and their applications in SystemVerilog.

What are SystemVerilog Loops?

A loop in programming repeats a block of code multiple times until a certain condition is met. A loop will continue running until the condition evaluates to true. If the loop doesn’t have a condition to stop, it can cause your simulation to hang indefinitely.

Here are the different types of SystemVerilog Loops:

Loop TypeDescription
foreverExecutes the block of code indefinitely until the simulation is manually stopped.
repeatRepeats the code a specific number of times.
whileRepeats the code as long as a condition is true.
forSimilar to the while loop but more compact and widely used.
do whileExecutes the code once before checking the condition to repeat it.
foreachIterates over all elements of an array without needing the array size.

1. forever Loop

The forever loop runs indefinitely. Without a termination condition, this can lead to the simulation hanging unless you add a time delay inside the loop. Below is an example that shows how a forever loop works:

Example: forever Loop

module tb;

  // A forever loop that runs indefinitely
  initial begin
    forever begin
      #5 $display("Hello, World!");
    end
  end

  // This initial block terminates the simulation after 50ns
  initial
    #50 $finish;

endmodule

In this example, the simulation runs for 50ns, displaying the message “Hello, World!” every 5 time units. Without $finish, the simulation would continue indefinitely.

Simulation Output:

Hello World!
Hello World!
Hello World!
...
Simulation complete via $finish(1) at time 50 NS

2. repeat Loop

The repeat loop repeats a block of code for a specific number of times. It’s often used when you need a loop to run a fixed number of iterations.

Example: repeat Loop

module tb;

  initial begin
    // Repeat the block 5 times
    repeat(5) begin
      $display("Hello, World!");
    end
  end

endmodule

Simulation Output:

Hello World!
Hello World!
Hello World!
Hello World!
Hello World!
Simulation complete.

3. while Loop

The while loop runs as long as a given condition is true. It’s very similar to the loops in C and Verilog.

Example: while Loop

module tb;
  bit clk;

  always #10 clk = ~clk;

  initial begin
    bit [3:0] counter;

    $display("Counter = %0d", counter);  // Initially counter is 0
    while (counter < 10) begin
      @(posedge clk);
      counter++;
      $display("Counter = %0d", counter);  // Counter increments
    end
    $display("Counter = %0d", counter);  // Counter = 10
    $finish;
  end
endmodule

Simulation Output:

Counter = 0
Counter = 1
Counter = 2
...
Counter = 10
Simulation complete via $finish(1) at time 190 NS

4. for Loop

The for loop is a compact form of the while loop. It allows you to specify the start value, condition, and increment in one line.

Example: for Loop

module tb;
  bit clk;

  always #10 clk = ~clk;

  initial begin
    bit [3:0] counter;

    $display("Counter = %0d", counter);  // Initially counter is 0
    for (counter = 2; counter < 14; counter = counter + 2) begin
      @(posedge clk);
      $display("Counter = %0d", counter);  // Counter increments
    end
    $display("Counter = %0d", counter);  // Counter = 14
    $finish;
  end
endmodule

Simulation Output:

Counter = 0
Counter = 2
Counter = 4
...
Counter = 14
Simulation complete via $finish(1) at time 110 NS

5. do while Loop

The do while loop first executes the block of code once before checking the condition. It guarantees that the code will run at least once.

Example: do while Loop

module tb;
  bit clk;

  always #10 clk = ~clk;

  initial begin
    bit [3:0] counter;

    $display("Counter = %0d", counter);  // Initially counter is 0
    do begin
      @(posedge clk);
      counter++;
      $display("Counter = %0d", counter);  // Counter increments
    end while (counter < 5);
    $display("Counter = %0d", counter);  // Counter = 5
    $finish;
  end
endmodule

Simulation Output:

Counter = 0
Counter = 1
Counter = 2
...
Counter = 5
Simulation complete via $finish(1) at time 90 NS

6. foreach Loop

The foreach loop is used to iterate over all elements in an array. You don’t need to manually calculate the array size or index variables.

Example: foreach Loop

module tb_top;
  bit [7:0] array [8];  // Create an array of size 8

  initial begin
    // Assign a value to each location in the array
    foreach (array[index]) begin
      array[index] = index;
    end

    // Display each value in the array
    foreach (array[index]) begin
      $display("array[%0d] = 0x%0d", index, array[index]);
    end
  end
endmodule

Simulation Output:

array[0] = 0x0
array[1] = 0x1
array[2] = 0x2
...
array[7] = 0x7
Simulation complete.

Conclusion

SystemVerilog provides a variety of looping constructs for different use cases. Understanding how and when to use these loops will help you write more efficient and readable code. Whether you need an infinite loop or a loop that runs for a specific number of iterations, there’s a SystemVerilog loop for every situation.

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