SystemVerilog Inheritance is a powerful feature in object-oriented programming (OOP) that allows one class to inherit the properties and methods of another class. This means you can create new classes based on existing ones, while still reusing the code and functionality of the original class. It helps developers extend classes with new features without modifying the original class. In this guide, we’ll break down the concept of inheritance in SystemVerilog, provide a simple code example, and explain key points in an easy-to-understand way.

What Is SystemVerilog Inheritance?

In SystemVerilog, inheritance allows you to create a new class (child class) based on an existing one (parent class). The child class inherits all the properties (variables) and methods (functions) of the parent class. However, the child class can also define its own unique properties and methods.

The main benefit of inheritance is that you can extend functionality without changing the original code. This keeps your code clean and makes it easier to manage. You can modify or add new features to the child class while still having access to the parent class features.

Basic Example of SystemVerilog Inheritance

Let’s look at an example to understand how inheritance works in SystemVerilog.

Parent Class: Packet

The Packet class defines an address property and a display method to show this address.

class Packet;
    int addr; // address of the packet

    // Constructor to initialize address
    function new (int addr);
        this.addr = addr;
    endfunction

    // Display method to show address
    function display ();
        $display ("[Base] addr=0x%0h", addr);
    endfunction
endclass

Child Class: ExtPacket

Now, we create a new class called ExtPacket that extends Packet. This child class will inherit the addr property and display() method from the parent class. Additionally, we will introduce a new property called data and a modified display() function to show both addr and data.

class ExtPacket extends Packet;
    int data; // New property for child class

    // Constructor for initializing both addr and data
    function new (int addr, int data);
        super.new(addr);  // Calls the parent class constructor
        this.data = data; // Initialize the new data property
    endfunction

    // Overridden display method to show both addr and data
    function display ();
        $display ("[Child] addr=0x%0h data=0x%0h", addr, data);
    endfunction
endclass

Key Points of SystemVerilog Inheritance

1. Inheritance allows the child class to inherit the properties and methods of the parent class.
2. Constructor in child class: The child class can call the parent class constructor using the super keyword.
3. Method Overriding: If both the parent and child class have a method with the same name, the method of the child class will be executed if invoked through the child class instance. However, if the method is called via the parent class instance, the parent class method will execute.
4. Object Handles: You can create objects for both parent and child classes and invoke their methods based on the object type.

Complete SystemVerilog Example: Parent and Child Classes in Action

Let’s combine everything in a SystemVerilog testbench to see how both parent and child classes work together.

module tb;
    Packet      baseClass;   // Parent class handle
    ExtPacket   subClass;    // Child class handle

    initial begin
        // Create a Packet object and display its address
        baseClass = new (32'hface_cafe);
        baseClass.display ();

        // Create an ExtPacket object and display both address and data
        subClass = new (32'hfeed_feed, 32'h1234_5678);
        subClass.display ();
    end
endmodule

Simulation Log:

After running the simulation, you’ll see the following log:

[Base] addr=0xfacecafe
[Child] addr=0xfeedfeed data=0x12345678

As you can see, the child class ExtPacket successfully overrides the display() method and shows both the address and data. The parent class Packet, on the other hand, only displays the address.

Understanding SystemVerilog Inheritance and Polymorphism

Inheritance becomes more complex when you assign a child class object to a parent class handle, or vice versa. This scenario is known as Polymorphism, and it allows for greater flexibility in your design. We will cover Polymorphism in more detail in another article, as it involves advanced concepts related to inheritance.

SystemVerilog Inheritance: Comparison of Parent and Child Classes

Here’s a quick comparison table that summarizes the differences between the parent and child classes:

Conclusion

SystemVerilog Inheritance allows you to build upon existing classes without changing their code. By using inheritance, you can create flexible and maintainable designs. Whether you’re building simple or complex systems, this feature can significantly improve the structure and organization of your code.

Remember that while inheritance is powerful, understanding the way method overriding works and how polymorphism can be applied will help you fully leverage this concept in SystemVerilog.