SystemVerilog inheritance is a feature of Object-Oriented Programming (OOP) that allows a new class to inherit properties and methods from an existing class. This makes it easy to reuse and extend functionality without modifying the original class. In other words, inheritance helps developers create new classes based on existing ones, while still maintaining access to the features of the parent class.

What is Inheritance in SystemVerilog?

In SystemVerilog, inheritance enables a subclass to inherit the attributes (properties) and behaviors (methods) of a parent class. By using inheritance, we can create more specific classes from general ones without altering the base class.

The subclass can also introduce new variables and methods, while still being able to use the inherited methods and properties from the parent class. This leads to cleaner, more maintainable code.

Example of SystemVerilog Inheritance

Let’s take a look at an example that demonstrates how SystemVerilog inheritance works.

Parent Class: Packet

The parent class defines basic properties and methods that the child class can inherit. Here’s how the Packet class is defined:

class Packet;
    int addr;

    // Constructor for Packet class
    function new (int addr);
        this.addr = addr;
    endfunction

    // Display function in Packet class
    function display ();
        $display ("[Base] addr=0x%0h", addr);
    endfunction
endclass

Child Class: ExtPacket

The child class ExtPacket inherits from Packet using the extends keyword. This class introduces a new property data and overrides the display() function. Here’s the ExtPacket class:

class ExtPacket extends Packet;
    // New variable in the child class
    int data;

    // Constructor for ExtPacket class
    function new (int addr, int data);
        super.new (addr);  // Call the parent class constructor
        this.data = data;
    endfunction

    // Display function in ExtPacket class
    function display ();
        $display ("[Child] addr=0x%0h data=0x%0h", addr, data);
    endfunction
endclass

How Inheritance Works in SystemVerilog

In the above example, the ExtPacket class inherits all properties and methods from the Packet class. When we create an object of ExtPacket, it will have both the addr property from the parent and the data property specific to the child class.

Parent and Child Class Behavior

If both the parent and child classes have a method with the same name, such as display(), the method that is called will depend on the type of object used. For instance, if you use a handle from the child class (ExtPacket), it will call the display() method from the child class. If you use a handle from the parent class (Packet), it will call the method from the parent class.

SystemVerilog Inheritance Example: Simulation Log Output

Here’s the code for the SystemVerilog testbench, where we test both classes:

module tb;
    Packet      bc;   // Handle for base class
    ExtPacket   sc;   // Handle for child class

    initial begin
        // Create Packet object
        bc = new (32'hface_cafe);
        bc.display ();

        // Create ExtPacket object
        sc = new (32'hfeed_feed, 32'h1234_5678);
        sc.display ();
    end
endmodule

Simulation Output

When running the simulation, you will see the following output:

[Base] addr=0xfacecafe
[Child] addr=0xfeedfeed data=0x12345678
ncsim: *W,RNQUIE: Simulation is complete.

This output shows that the display() function from the parent class Packet is called when using the base class handle, and the display() function from the child class ExtPacket is called when using the child class handle.

Handling Child Class Instances with Base Class Handles

The situation becomes more complex when you try to assign an instance of the child class to a base class handle, or vice versa. This concept is explored further in Polymorphism, which enables objects to be treated as instances of their parent class. Understanding this concept is key to mastering SystemVerilog inheritance.

Comparison Table: Parent vs Child Class Inheritance

Key Benefits of SystemVerilog Inheritance

• Code Reusability: Inheritance allows the reuse of existing functionality, which saves development time.
• Scalability: You can extend the functionality of parent classes by adding new features in child classes.
• Maintainability: Changes to the parent class can be automatically reflected in all child classes, making the code easier to maintain.