The inside operator in SystemVerilog Constraint helps check if a variable value lies within a specified range or a set of values. You can use it in both constraints and conditional statements like if or else. It simplifies range checking and improves code readability.
Syntax of inside Operator
The general syntax for the inside operator is:
<variable> inside {<values or range>}
You can also invert it by using the ! symbol:
!(<variable> inside {<values or range>})
Examples of Using inside Operator
Checking a Set of Values
For example, to check if a variable m_var is one of several values, use:
m_var inside {4, 7, 9} // Checks if m_var is 4, 7, or 9
Checking a Range of Values
To check if a variable m_var is between a range of values, use:
m_var inside {[10:100]} // Checks if m_var is between 10 and 100
Using inside in Conditional Statements
You can use the inside operator in both if-else and ternary operators. The following example uses inside to assign a value to a flag and display messages based on whether m_data lies within the range of 4 to 9.
module tb;
bit [3:0] m_data;
bit flag;
initial begin
for (int i = 0; i < 10; i++) begin
m_data = $random;
// Ternary operator
flag = m_data inside {[4:9]} ? 1 : 0;
// Using "if-else"
if (m_data inside {[4:9]})
$display("m_data=%0d INSIDE [4:9], flag=%0d", m_data, flag);
else
$display("m_data=%0d outside [4:9], flag=%0d", m_data, flag);
end
end
endmodule
Simulation Log Output:
m_data=4 INSIDE [4:9], flag=1
m_data=1 outside [4:9], flag=0
m_data=9 INSIDE [4:9], flag=1
...
Using inside in SystemVerilog Constraint
The inside operator simplifies constraints by making them shorter and more readable. For example, you can constrain a variable to specific values using inside:
class ABC;
rand bit [3:0] m_var;
// Constrain m_var to values 3, 4, 5, 6, or 7
constraint c_var { m_var inside {[3:7]}; }
endclass
module tb;
initial begin
ABC abc = new();
repeat (5) begin
abc.randomize();
$display("abc.m_var = %0d", abc.m_var);
end
end
endmodule
Simulation Log Output:
abc.m_var = 7
abc.m_var = 6
abc.m_var = 6
abc.m_var = 3
abc.m_var = 4
Inverted inside
To specify that a variable should not lie within a particular range, use the inverted inside operator with the ! symbol. The following example shows how to constrain a variable m_var to be outside the range of 3 to 7:
class ABC;
rand bit [3:0] m_var;
// Inverted inside: Constrain m_var to be outside 3 to 7
constraint c_var { !(m_var inside {[3:7]}); }
endclass
module tb;
initial begin
ABC abc = new();
repeat (5) begin
abc.randomize();
$display("abc.m_var = %0d", abc.m_var);
end
end
endmodule
Simulation Log Output:
abc.m_var = 1
abc.m_var = 12
abc.m_var = 0
abc.m_var = 14
abc.m_var = 10
Practical Example: Randomizing Memory Addresses
The inside operator is useful when you need to randomize memory addresses that lie within a specific range. For instance, if you want to randomize an address that falls within the data part of a memory range, you can use inside as follows:
class Data;
rand bit [15:0] m_addr;
// Constrain m_addr to the data memory range
constraint c_addr { m_addr inside {[16'h4000:16'h4fff]}; }
endclass
module tb;
initial begin
Data data = new();
repeat (5) begin
data.randomize();
$display("addr = 0x%0h", data.m_addr);
end
end
endmodule
Simulation Log Output:
addr = 0x48ef
addr = 0x463f
addr = 0x4612
addr = 0x4249
addr = 0x4cee
Summary
The inside operator in SystemVerilog Constraint helps you easily check if a variable is within a specific range or set of values. It can be used in constraints, conditional statements, and other logical checks. You can also invert its behavior with the ! symbol to check if a value falls outside a range. This operator makes your code more readable, compact, and efficient.
