SystemVerilog is an extension of Verilog that introduces Object-Oriented Programming (OOP) concepts. One of the core features of OOP in SystemVerilog is the class. A class is a user-defined data type that allows you to encapsulate both data (properties) and functions (methods). In this article, we will explain how SystemVerilog classes work, their key features, and provide code examples to help you understand their use.

What is a SystemVerilog Class?

A SystemVerilog class is a blueprint for creating objects. It encapsulates both properties (variables) and methods (functions or tasks) that can operate on those properties. Here’s a simple example of a SystemVerilog class:

class myPacket;
    bit [2:0] header;
    bit encode;
    bit [2:0] mode;
    bit [7:0] data;
    bit stop;

    function new (bit [2:0] header = 3'h1, bit [2:0] mode = 5);
        this.header = header;
        this.encode = 0;
        this.mode   = mode;
        this.stop   = 1;
    endfunction

    function display ();
        $display("Header = 0x%0h, Encode = %0b, Mode = 0x%0h, Stop = %0b",
                 this.header, this.encode, this.mode, this.stop);
    endfunction
endclass

Key Points to Note:

1. Constructor (new function):
   • The new function is called the constructor. It initializes the class object when created.
   • It is automatically invoked when an object of the class is created.
2. The this keyword:
   • this refers to the current instance of the class. It helps access the properties and methods within the class.
3. The display function:
   • The display function is used to show the values of the class properties. It does not consume simulation time since it’s a function.
4. Default Constructor Arguments:
   • The new function has default arguments, which means if no arguments are passed, default values are assigned to the properties.

Creating and Using Objects

To use the class, you must create an object. The object is used as a handle to access the properties and methods of the class.

module tb_top;
    myPacket pkt0, pkt1;

    initial begin
        // Create object with custom values
        pkt0 = new(3'h2, 2'h3);
        pkt0.display();

        // Create object with default values
        pkt1 = new();
        pkt1.display();
    end
endmodule

Simulation Log Output:

Header = 0x2, Encode = 0, Mode = 0x3, Stop = 1
Header = 0x1, Encode = 0, Mode = 0x5, Stop = 1

Creating an Array of Classes

You can create an array of objects just like any other data type. Here’s how you can create and initialize an array of class objects:

module tb_top;
    myPacket pkt0 [3];

    initial begin
        for (int i = 0; i < $size(pkt0); i++) begin
            pkt0[i] = new();
            pkt0[i].display();
        end
    end
endmodule

Simulation Log Output:

Header = 0x1, Encode = 0, Mode = 0x5, Stop = 1
Header = 0x1, Encode = 0, Mode = 0x5, Stop = 1
Header = 0x1, Encode = 0, Mode = 0x5, Stop = 1

Since each myPacket object is created using the default constructor, default values are assigned automatically.

Inheritance in SystemVerilog Classes

One of the key features of Object-Oriented Programming is inheritance. Inheritance allows you to create a new class that shares the properties and methods of an existing class. You can extend a class by using the extends keyword. Here’s an example:

class networkPkt extends myPacket;
    bit parity;
    bit [1:0] crc;

    function new();
        super.new();  // Call the constructor of the base class (myPacket)
        this.parity = 1;
        this.crc = 3;
    endfunction

    function display();
        super.display();  // Display values from the base class
        $display("Parity = %0b, CRC = 0x%0h", this.parity, this.crc);
    endfunction
endclass

Key Features of Inheritance:

• extends keyword: This is used to inherit from the base class. The derived class (networkPkt) gets all properties and methods of the base class (myPacket).
• super keyword: This is used to call the methods or constructor of the base class. It’s helpful when you want to extend the functionality of the inherited methods.

Abstract Classes in SystemVerilog

An abstract class is a class that cannot be instantiated directly. Instead, it serves as a base class that other classes can inherit from. You can create an abstract class using the virtual keyword. Here’s an example:

// Creation of base class object is invalid
virtual class Base;
    bit [7:0] data;
    bit enable;
endclass

// Creation of child class object is valid
class Child extends Base;
    // User-defined properties and methods
endclass

Why Use Abstract Classes?

• Enforcing Structure: Abstract classes allow you to define a common structure while preventing the creation of objects directly from the base class.
• Ensuring Consistency: By inheriting from an abstract class, you ensure that all derived classes follow the same structure and behavior.

Conclusion

SystemVerilog classes are a powerful feature that brings object-oriented programming concepts to hardware design and verification. Classes help you encapsulate data and behaviors, improve code reusability, and create more modular and maintainable code. By using inheritance and abstract classes, you can build complex systems that are easy to extend and maintain.

Here’s a summary of the key points:

By understanding these features, you can better leverage SystemVerilog classes in your design and verification tasks.