SystemVerilog allows randomizing array data structures like static arrays, dynamic arrays, and queues. To enable randomization, the variable must be declared using the rand or randc keyword. In this article, we’ll explore how randomization works with these different types of arrays in SystemVerilog.

1. Randomizing Static Arrays in SystemVerilog

Randomization for static arrays in SystemVerilog is straightforward. Static arrays are arrays where the size is fixed at the time of declaration. You can randomize the elements of static arrays just like any other variable.

Example of Randomizing Static Arrays:

class Packet;
  rand bit [3:0] s_array[7];  // Declare a static array with "rand"
endclass

module tb;
  Packet pkt;

  // Create a new packet, randomize it and display contents
  initial begin
    pkt = new();
    pkt.randomize();
    $display("queue = %p", pkt.s_array);
  end
endmodule

In this example, we declare a static array s_array with 7 elements. Each element is of type bit[3:0]. The array is randomized using the randomize() function, and the contents are displayed using $display.

Simulation Output:

queue = '{'hf, 'hf, 'h2, 'h9, 'he, 'h4, 'ha}

2. Randomizing Dynamic Arrays in SystemVerilog

Dynamic arrays differ from static arrays because their size is not fixed. Dynamic arrays can grow in size as new elements are added during runtime. Let’s look at an example where a dynamic array is randomized.

Example of Randomizing Dynamic Arrays:

class Packet;
  rand bit [3:0] d_array[];  // Declare a dynamic array with "rand"

  // Constrain the size of dynamic array between 5 and 10
  constraint c_array { d_array.size() > 5; d_array.size() < 10; }

  // Constrain the value of each element to equal its index
  constraint c_val { foreach (d_array[i]) 
    d_array[i] == i; }

  // Utility function to display dynamic array contents
  function void display();
    foreach (d_array[i])
      $display ("d_array[%0d] = 0x%0h", i, d_array[i]);
  endfunction
endclass

module tb;
  Packet pkt;

  // Create a new packet, randomize it, and display contents
  initial begin
    pkt = new();
    pkt.randomize();
    pkt.display();
  end
endmodule

In this case, we declare a dynamic array d_array[] and apply two constraints:

1. The size of the dynamic array is constrained to be between 5 and 10.
2. Each element of the dynamic array is constrained to match its index value.

Simulation Output:

d_array[0] = 0x0
d_array[1] = 0x1
d_array[2] = 0x2
d_array[3] = 0x3
d_array[4] = 0x4
d_array[5] = 0x5
d_array[6] = 0x6
d_array[7] = 0x7
d_array[8] = 0x8

3. Randomizing Queues in SystemVerilog

Queues are another important data structure in SystemVerilog. A queue is similar to a dynamic array, but it has the added ability to change its size dynamically during runtime. Let’s explore how to randomize a queue.

Example of Randomizing Queues:

class Packet;
  rand bit [3:0] queue[$];  // Declare a queue with "rand"

  // Constrain the size of the queue between 5 and 10
  constraint c_array { queue.size() == 4; }
endclass

module tb;
  Packet pkt;

  // Create a new packet, randomize it, and display contents
  initial begin
    pkt = new();
    pkt.randomize();
    // Tip: Use %p to display arrays
    $display("queue = %p", pkt.queue);
  end
endmodule

In this example, we declare a queue queue[$] of type bit[3:0] and randomize it using the randomize() function. The size of the queue is constrained to be 4.

Simulation Output:

queue = '{'hf, 'hf, 'h2, 'h9}

Key Takeaways

• Static Arrays: Their size is fixed during declaration, and randomization is straightforward.
• Dynamic Arrays: Their size can change dynamically at runtime. Constraints can be applied to control the array size and element values.
• Queues: Similar to dynamic arrays but with the added capability to resize at runtime. Constraints can also be applied to queues.

Table: Comparison of Array Types in SystemVerilog

Conclusion

SystemVerilog randomization allows for flexible handling of arrays, whether static, dynamic, or queues. By applying constraints to these arrays, you can control the size and values of the array elements during simulation, ensuring accurate and meaningful randomization.

This guide provides simple and clear examples for understanding how to randomize different array types in SystemVerilog effectively. Whether you’re working with fixed-size static arrays or resizable dynamic arrays and queues, you now know how to implement randomization and constraints for all of them.