In SystemVerilog, an abstract class is a class that cannot be directly instantiated. If a class is declared as virtual, it is considered an abstract class. SystemVerilog uses abstract classes to enforce the inheritance of base classes. These classes are useful for guiding test case developers to always extend a base class to form other classes.

What is a SystemVerilog Abstract Class?

An abstract class in SystemVerilog is declared using the virtual keyword. These classes cannot be instantiated directly but can be extended by other classes. This enforces a design rule, ensuring that the abstract class serves as a base for subclasses.

Example of Declaring a Virtual (Abstract) Class

virtual class BaseClass;
    int data;

    function new();
        data = 32'hc0de_c0de;
    endfunction
endclass

Here, we declare a virtual class named BaseClass with a data member and a constructor. Since it’s a virtual class, it cannot be instantiated directly.

Instantiating Abstract Classes: What Happens?

If you try to instantiate a virtual (abstract) class directly, SystemVerilog will throw an error. This is because abstract classes are meant to be extended, not instantiated.

Example of Error When Instantiating an Abstract Class

virtual class BaseClass;
    int data;

    function new();
        data = 32'hc0de_c0de;
    endfunction
endclass

module tb;
    BaseClass base; // Error: Cannot instantiate virtual class directly.
    initial begin
        base = new();
        $display("data = 0x%0h", base.data);
    end
endmodule

Simulation Log:

ncsim> run
Error: An abstract (virtual) class cannot be instantiated.

In the simulation log, we see that the simulator reports an error because we tried to instantiate the abstract class BaseClass directly.

Extending Abstract Classes

Although abstract classes cannot be instantiated, they can be extended using the extends keyword. This allows us to create subclasses that can be instantiated.

Example of Extending an Abstract Class

virtual class BaseClass;
    int data;

    function new();
        data = 32'hc0de_c0de;
    endfunction
endclass

class ChildClass extends BaseClass;
    function new();
        data = 32'hfade_fade;
    endfunction
endclass

module tb;
    ChildClass child;
    initial begin
        child = new();
        $display("data = 0x%0h", child.data);
    end
endmodule

Simulation Log:

ncsim> run
data = 0xfadefade
ncsim: *W,RNQUIE: Simulation is complete.

As shown in the simulation log, the subclass ChildClass extends BaseClass and can be instantiated successfully.

Understanding Pure Virtual Methods

In SystemVerilog, abstract classes can have pure virtual methods. These methods are declared with the pure keyword and only require a function prototype. The actual implementation of the method is provided in the subclass.

Example of Declaring and Implementing a Pure Virtual Method

virtual class BaseClass;
    int data;

    pure virtual function int getData();
endclass

class ChildClass extends BaseClass;
    virtual function int getData();
        data = 32'hcafe_cafe;
        return data;
    endfunction
endclass

module tb;
    ChildClass child;
    initial begin
        child = new();
        $display("data = 0x%0h", child.getData());
    end
endmodule

Simulation Log:

ncsim> run
data = 0xcafecafe
ncsim: *W,RNQUIE: Simulation is complete.

In this example, the pure virtual method getData() is declared in the BaseClass and implemented in the ChildClass. The simulation shows that the method works as expected.

Comparison: Abstract Class vs. Regular Class

Here is a comparison between an abstract class (virtual class) and a regular class in SystemVerilog:

This table helps clarify the key differences between abstract and regular classes in SystemVerilog.

Conclusion

In this article, we explored the concept of SystemVerilog Abstract Class. We learned how abstract classes cannot be instantiated directly and must be extended by subclasses. We also covered pure virtual methods, which allow subclasses to implement specific functionality. Abstract classes are an essential feature in SystemVerilog for enforcing a clean and maintainable object-oriented design.

By using abstract classes, you ensure that your code is more modular and reusable. It’s a powerful tool for any SystemVerilog programmer looking to structure their verification environment efficiently.