A Ring Counter is a type of Shift Register used in digital circuits. It operates similarly to a shift counter, with one key difference: the output of the last flip-flop in the counter is connected back to the input of the first flip-flop, forming a closed loop. This is what distinguishes a Ring Counter from a standard Shift Register, where the output is typically taken from the last flip-flop without feeding it back. In this article we gonna differentiate the Straight and Twisted Ring Counter along with their code.

Key Concept of Ring Counter: Number of States

The number of states in a Ring Counter depends on the number of flip-flops used. For example, to design a 4-bit Ring Counter, you would need 4 flip-flops. Here’s a quick overview:

• Number of states in a Ring Counter = Number of flip-flops used
• For a 4-bit Ring Counter, you need 4 flip-flops.

Working of the 4-Bit Ring Counter

In a 4-bit ring counter, all flip-flops receive the same clock pulse (CLK) simultaneously, making it a Synchronous Counter. Additionally, we use an Overriding Input (ORI) for each flip-flop, with two important signals:

• Preset (PR): When this signal is 0, the output is set to 1.
• Clear (CLR): When this signal is 0, the output is set to 0.

Both PR and CLR are active-low signals, meaning they work when their values are 0.

Key Conditions:

• PR = 0, Output Q = 1
• CLR = 0, Output Q = 0

These conditions are fixed and do not depend on the input D or the Clock Pulse (CLK).

Step-by-Step Working

1. Preset 1 at FF-0: Initially, we apply the Preset (PR) signal to flip-flop FF-0, setting its output to 1. For the other flip-flops (FF-1, FF-2, FF-3), the Clear (CLR) signal sets their outputs to 0. The initial state is 1 0 0 0.
2. Clock Pulse: Once the preset is applied, the Clock Pulse (CLK) triggers the flip-flops, shifting the 1 from FF-0 to the next flip-flop in each cycle, creating a continuous ring.

States in a 4-Bit Ring Counter

The 4-bit Ring Counter will cycle through 4 different states:

• 1 0 0 0
• 0 1 0 0
• 0 0 1 0
• 0 0 0 1

These 4 states will repeat in a loop, allowing the counter to function as intended.

Types of Ring Counter

There are two main types of ring counters: Straight Ring Counter and Twisted Ring Counter.

Straight Ring Counter (One Hot Counter)

In the Straight Ring Counter, the output of the last flip-flop is connected to the input of the first flip-flop, creating a loop. This counter circulates a single 1 (or 0) bit around the ring.

• Preset (PR) is used for the first flip-flop, and the Clock (CLK) is applied to the last three flip-flops.

Twisted Ring Counter (Johnson Counter)

The Twisted Ring Counter is also known as a Switch-Tail Ring Counter or Walking Ring Counter. In this type, the complement of the output of the last flip-flop is fed back into the first flip-flop. This creates a pattern of ones and zeros circulating around the ring.

• In the Twisted Ring Counter, the Clock (CLK) is applied to all the flip-flops, and the number of states is twice the number of flip-flops.

Comparing Straight and Twisted Ring Counters

Verilog Code for a 4-Bit Straight Ring Counter

Below is the Verilog code for a 4-bit Straight Ring Counter:

module ring_counter #(parameter WIDTH = 4)
(
  input clk,
  input rstn,
  output reg [WIDTH-1:0] out
);

always @(posedge clk) begin
  if (!rstn)
    out <= 1;  // Set output to 1 when reset is active
  else begin
    out[WIDTH-1] <= out[0];  // Shift the '1' to the next flip-flop
    for (int i = 0; i < WIDTH-1; i = i + 1) begin
      out[i] <= out[i+1];  // Shift the outputs of other flip-flops
    end
  end
end
endmodule

Testbench for the 4-Bit Straight Ring Counter

Here is the testbench that simulates the 4-bit Ring Counter:

module tb;
  parameter WIDTH = 4;

  reg clk;
  reg rstn;
  wire [WIDTH-1:0] out;

  // Instantiate the ring counter
  ring_counter u0 (
    .clk(clk),
    .rstn(rstn),
    .out(out)
  );

  // Generate clock signal with period of 20 time units
  always #10 clk = ~clk;

  initial begin
    {clk, rstn} <= 0;

    $monitor ("T=%0t out=%b", $time, out);  // Display output at each time step

    // Apply reset and wait for the counter to start
    repeat (2) @(posedge clk);
    rstn <= 1;
    repeat (15) @(posedge clk);  // Wait for 15 clock cycles
    $finish;  // End the simulation
  end
endmodule

Verilog Code for a 4-Bit Twisted Ring Counter (Johnson Counter)

Now, let’s look at the Verilog code for a 4-bit Twisted Ring Counter (Johnson Counter). In this counter, the complement of the output of the last flip-flop is fed back into the first flip-flop, creating a more complex sequence of ones and zeros.

module twisted_ring_counter #(parameter WIDTH = 4)
(
  input clk,
  input rstn,
  output reg [WIDTH-1:0] out
);

always @(posedge clk) begin
  if (!rstn)
    out <= {WIDTH{1'b0}};  // Reset all outputs to 0
  else begin
    out[WIDTH-1] <= ~out[0];  // Invert the first flip-flop output and feed it back to the last flip-flop
    for (int i = 0; i < WIDTH-1; i = i + 1) begin
      out[i] <= out[i+1];  // Shift the outputs of other flip-flops
    end
  end
end
endmodule

Testbench for the 4-Bit Twisted Ring Counter

Here’s the testbench to simulate the Twisted Ring Counter (Johnson Counter):

module tb_twisted_ring;
  parameter WIDTH = 4;

  reg clk;
  reg rstn;
  wire [WIDTH-1:0] out;

  // Instantiate the twisted ring counter (Johnson counter)
  twisted_ring_counter u0 (
    .clk(clk),
    .rstn(rstn),
    .out(out)
  );

  // Generate clock signal with period of 20 time units
  always #10 clk = ~clk;

  initial begin
    {clk, rstn} <= 0;

    $monitor ("T=%0t out=%b", $time, out);  // Display output at each time step

    // Apply reset and wait for the counter to start
    repeat (2) @(posedge clk);
    rstn <= 1;
    repeat (15) @(posedge clk);  // Wait for 15 clock cycles
    $finish;  // End the simulation
  end
endmodule

Conclusion

Both the Straight Ring Counter and the Twisted Ring Counter (Johnson Counter) are useful in digital design for generating cyclic patterns. The Straight Ring Counter circulates a single bit (1 or 0), while the Twisted Ring Counter creates a more complex sequence of bits, making it suitable for different types of applications.