In this Routing Cheatsheet, you’ll find a quick yet comprehensive overview of routing concepts, objectives, constraints, and best practices used in modern chip design. Whether you’re a beginner or an experienced physical design engineer, this guide will help you recall key routing principles essential for successful tape-out.
Purpose & Place in Flow
- Purpose: Establishes all physical interconnections while meeting timing, power, SI, and DRC constraints.
- Place in Flow:
Floorplanning → Placement → CTS → Routing → Post-Route Opt. → Signoff - Impact: Direct effect on performance, power, area, and yield
Routing Stages
- Global Routing
- Divide chip into G-cells
- Generate routing guides & congestion maps
- Assign nets to regions & layers
- Track Assignment
- Map nets to exact tracks in guides
- Minimize vias & follow preferred directions
- Detailed Routing
- Generate final wire shapes + via placements
- Must satisfy all DRC, antenna, density rules
- Produces tape-out quality layout
Objectives of Routing
- ✅ Connectivity Completion (no opens/shorts)
- ✅ Timing Closure (RC parasitics within setup/hold limits)
- ✅ Power Optimization (low IR drop & dynamic loss)
- ✅ Crosstalk Reduction (noise & delay mitigation)
- ✅ DRC Compliance (manufacturability)
- ✅ Reliability (avoid EM & IR issues)
Key DRC Rules
- Min Rules: width, spacing, area, via enclosure, cut spacing
- EOL (End-of-Line): spacing at wire ends
- PRL (Parallel Run Length): spacing for long parallels
- Antenna Rules: prevent plasma damage
- Multi-Patterning: color-aware routing (<20nm)
- Density Rules: uniform metal density (CMP-friendly)
Key Concepts
- Preferred Directions: alternate H/V layers → less congestion
- Routing Grids: defines available track capacity per G-cell
- Vias: single-cut, multi-cut, stacked → redundant vias = EM safe
- NDR (Non-Default Rules): wider wires for clocks/high-speed nets
- Shielding: ground lines alongside critical nets
Congestion Management
- Use congestion maps after global routing
- Fix hotspots by:
- Spreading standard cells
- Adding blockages/halos
- Using higher metal layers
- Detour routing
Signal Integrity (SI)
- Crosstalk Noise: aggressor induces voltage on victim
- Crosstalk Delay: alters effective timing
- Fixes:
- Increase spacing
- Shield with ground nets
- Use NDRs
- Stagger switching
Special Net Routing
| Net Type | Method |
|---|---|
| Clock Nets | Wide wires, upper metals, shielding, balanced skew |
| Power/Ground | Mesh/straps/rings, redundant vias, wide metals |
| High-Fanout Nets | Buffered trees, balanced delays |
Advanced Node Challenges
- Multi-patterning: requires coloring
- EUV Litho: fewer masks but strict DRC
- FinFET: track-based routing only
- High RC parasitics: accurate extraction essential
Post-Routing Steps
- RC Extraction (SPEF)
- STA with real parasitics
- SI Analysis (crosstalk/noise)
- Antenna Fixing (diodes/jumpers)
- ECO Routing (incremental fixes)
- Signoff Checks (DRC/LVS)
Power & IR Drop Considerations
- Ensure power grid-aware routing
- Use voltage drop maps
- Add redundant vias & widen power nets
- Insert decaps for stability
Best Practices
- Assign critical nets to upper metals early
- Reserve routing blockages
- Apply NDR rules early
- Use incremental fixes for ECO
- Validate congestion immediately after global routing
Common Issues
- DRC violations (spacing, EOL, min area)
- Antenna rule failures
- Crosstalk-induced timing violations
- IR drop failures on PG nets
- Timing regressions post-routing
Useful Tool Commands
Cadence Innovus
routeDesign ; Full routing
checkRoute ; Detect violations
reportCongestion ; Congestion map
Synopsys ICC2
route_auto ; Automated routing
report_congestion ; Analyze congestion
fix_antenna ; Antenna fixes
Routing QoR Metrics
- Total wirelength
- Via count
- Timing slack post-routing
- DRC violation count
- Congestion %
Common Interview Questions
- Difference between global vs detailed routing?
- What are antenna violations & fixes?
- Why use NDR for clocks?
- What is multi-patterning?
- How do you handle congestion hotspots?
