Power planning in VLSI design has become increasingly important as technology has advanced, particularly in compact devices like earbuds and smartwatches. While designers once primarily focused on chip size and speed, managing power efficiently is now crucial. Effective power usage not only extends battery life but also enhances overall performance.
Key Components of Power Planning in VLSI Designs
Power planning ensures that electricity flows smoothly from the power source to the chip’s components. This flow is known as the Power Distribution Network (PDN). The PDN consists of several elements:
| Component | Description |
| Power Pads | These connect to the outside power source and feed power to the chip. |
| Trunks | Nets that connect power pads to core rings. |
| Core Rings | Rings surrounding the core area that supply power to stripes. |
| Power Stripes | These run above the core area and connect to the core rings. |
| Power Rails | They deliver power directly to the chip’s components. |
Inputs and Outputs of Power Planning
To create an effective Power Planning in VLSI Designs, designers use various inputs and produce specific outputs.
Inputs:
- Netlist: A list showing how components connect.
- Timing Libraries: Data on how long signals take to travel.
- Physical Libraries: Information about the chip’s physical design.
- RC Coefficients: Values that describe resistance and capacitance.
- Standard Design Constraints (SDC): Guidelines for design rules.
- Power Formats: UPF or CPF help manage multiple voltage areas in a design.
Outputs:
- DEF File: A layout that shows the power distribution network.
Types of Power Consumption
Understanding power consumption helps designers avoid problems. There are two main types:
- Static Power Dissipation: This occurs when the chip is not active, mainly due to leakage currents in the transistors.
- Dynamic Power Dissipation: This happens during the operation of the chip. It can be broken down into two parts:
- Switching Power: Calculated as: Pswitch​=α ⋅ f⋅ CLoad​ ⋅ Vdd2​
- Short Circuit Power: Represented as Pshort circuit​ = tsc​ ⋅ Vdd​ ⋅ Ipeak​
How Power Planning in VLSI Works
Power Planning in VLSI involves creating a system to provide electricity to all parts of the chip. Designers lay out power and ground nets on metal layers. They also need to calculate how many power pins are necessary, how wide the power rings and stripes should be, and how to manage voltage drops.
Important Considerations:
- Sanity Checks: Verify the power connections and ensure that the power mesh is properly linked to the chip components.
- DRC Checks: Perform Design Rule Checks to ensure compliance with design standards.
What is Power Gating?
Power gating is a technique used to turn off parts of the circuit that are not in use, reducing leakage power. When the SLEEP signal is active, sleep transistors are off, breaking the direct connection between power rails and ground, which minimizes power waste.
Electromigration (EM) Flow and Considerations
Electromigration refers to the movement of metal atoms due to high current densities. To manage EM, tools analyze average current for power nets during static simulations and consider worst-case scenarios during dynamic simulations. Designers use specific TCL commands to calculate EM effects based on current types (Ipeak, Irms, or Iavg).
Key Terms Related to Signal EM
- Irms / Ilimit Ratio: This ratio helps ensure that the calculated Irms stays below the foundry-specified limits to prevent overheating.
- Effective Frequency: Represents how often a signal toggles. It’s usually half the clock frequency for data lines.
- DeltaTemp: Indicates the maximum allowable temperature increase due to current flow. It is calculated from the resistance and the current.
Common Causes of Signal EM
- High Fanout Net: When many components connect to one driver, it draws a lot of current and generates heat.
- Driver Size: Larger driver cells cause more current, increasing risk.
- Fast Transitions: High-speed signals can lead to collisions, damaging the metal structure.
- Long Nets: Longer interconnects increase resistance and heat.
Solutions for Signal EM
Manual Fixes:
- Driver Downsizing: Reduce driver sizes to lower current density without impacting performance.
- Non-Default Rules (NDR): Increase metal widths for better current handling.
- Inserting Buffers: Break long connections to reduce resistance while maintaining timing.
- Routing on Higher Layers: Use less resistive layers for better power delivery.
- Using Multi-Cut Vias: Increase connection area to reduce resistance.
- Breaking High Fanouts: Split fanouts to lower current draw.
Automatic Fixes:
- NDR Aware PNR: The placement engine uses more space for nets to allow for NDR applications.
- Hold Fixing: Adding buffers during design can break nets and reduce EM violations.
Methods to Resolve EM Issues
- Increase the cross-sectional area of metal layers.
- Create parallel paths for current flow.
- Adjust driver strengths based on load requirements.
Dynamic IR Drop
Input Files for Dynamic Analysis
- LEF: Contains pin and boundary information.
- DEF: Shows the logical and physical connections.
- LIB: Provides cell properties.
- SPEF: Contains parasitic resistance and capacitance values.
- ploc: Holds pad location data.
- Redhawk Tech File: Details resistance and EM limits.
- APL Files: Characterization data for cells.
- VCD File: Tracks net activity and power peaks.
- GDSII File: Physical layout details for accurate analysis.
- Technology File: Contains metal layer specifications.
- GDS Layer Map File: Links GDS layer numbers to LEF names.
- Global System Requirement File (GSR): Specifies operational conditions and analysis parameters.
What’s Inside the STA File?
- Slew: Time taken to transition from low to high states.
- Timing Window: Range in which a gate can switch.
- Clock Domain: The clock under which a logic cell operates.
- Instance Frequency: Charging and discharging time for cells.
RedHawk Outputs
- Voltage drop contour maps.
- Electro-migration analysis reports.
- Power density and average current maps.
- Detailed reports of power, voltage, and current data.
PDN Checks
Important Checks Include:
- Opens: Ensure all connections are intact.
- Missing Vias: Verify that vias are present and correctly placed.
- Cell Clustering: Check for optimal cell arrangement.
- IR Hotspots: Identify areas of excessive power drop.
Using Multi-Cut Vias
Multi-cut vias provide several advantages over single-cut vias:
| Advantage | Explanation |
| Increased Reliability | More connections mean that if one fails, others remain. |
| Lower Resistance | Multiple paths reduce overall resistance, enhancing performance. |
Conclusion
Power planning in VLSI is critical, especially for modern portable devices. By understanding the Power Distribution Network and different power dissipation types, designers can create efficient designs that enhance battery life and overall performance.
