Placement in VLSI is a key phase in the physical design of Very Large Scale Integration (VLSI) chips. This process involves arranging all standard cells within the chip’s core area. The placement tool optimizes not only the positioning of these cells but also the overall design for factors like timing, congestion, and power efficiency. This article will explain the placement process in simple, clear terms, focusing on the goals, inputs, techniques, and checks involved.
What is Placement in VLSI?
Placement in VLSI refers to the process of positioning standard cells within the designated area of a VLSI chip. The tool responsible for placement aims to optimize the design, ensuring that the arrangement of cells meets essential criteria such as timing, power consumption, and routing efficiency.
Goals of Placement in VLSI
The primary goals of Placement in VLSI include:
- Optimize Timing, Area, and Power: Ensure that the design performs efficiently in terms of speed and power usage.
- Minimize Congestion: Reduce congestion to minimize areas where routing tracks are too crowded, as this can lead to issues during the routing phase.
- Control Cell and Pin Density: Maintain a balanced distribution of cells and pins to prevent timing-related problems.
- Avoid Timing Violations: Ensure that the design does not exceed allowed timing limits (timing DRVs).
Inputs Required for Placement in VLSI
Before the placement stage several key inputs are necessary:
| Input | Description |
| Netlist | A detailed list of connections between different components. |
| Physical Libraries (.lef) | Libraries that define the physical characteristics of standard cells. |
| Floorplan DEF File | A file that outlines the layout of the design area. |
| Timing Libraries (.lib) | Libraries containing timing information for various cells. |
| Multi-Mode Multi-Corner (MMMC) | Data that considers different operating conditions for the design. |
| RC Corners | Information about resistance and capacitance in different scenarios. |
| SDC File | Standard delay format file containing timing constraints. |
| UPF File | Used for designs with multiple voltage domains, defining power intent. |
Steps in the Placement in VLSI Process
Placement in VLSI can be divided into three main phases:
Pre-Placement
In this initial step, the tool conducts several checks to ensure everything is in order. This includes:
- Cleaning the Netlist: Ensuring there are no errors or inconsistencies.
- Validating the Floorplan: Confirming the floorplan is accurate.
- Proper Pin Placement: Checking that all pins are correctly positioned.
- Fixing Macros and Pre-Placed Cells: Ensuring these cells are in fixed positions.
- Checking Power Routes: Making sure there are no Design Rule Check (DRC) violations.
Pre-placement also involves positioning necessary physical-only cells, such as endcap cells and well taps.
Placement
The placement phase involves several critical steps:
Global Placement
During global placement, the tool positions all standard cells within the core area. This step prioritizes minimizing the total interconnect length without enforcing strict design rules, allowing some overlaps. After this step, trial routing can be performed to estimate congestion.
Early Global Routing (Trail Routing)
The tool performs trial routing by dividing the metal layers into grid cells (GCells). Each GCell contains routing tracks that help assess potential congestion and calculate parasitic effects like resistance and capacitance. Understanding congestion is crucial; if there are more required routing tracks than available, the area is termed congested.
Legalization
This step involves adjusting the positions of standard cells to eliminate any overlaps and ensure compliance with design rules. The tool spreads out cells in areas of high density to avoid power issues and ensures that all cells align correctly with power rails.
Post Placement
After placement, the tool verifies that all design timing requirements are met. This includes checking for:
- Worst Negative Slack (WNS): A measure of timing violations.
- Total Negative Slack (TNS): The total amount of timing violations in the design.
- Tie Cell Placement: Adding tie cells to connect any unused inputs to power (VDD) or ground (VSS).
Specialized Placement in VLSI Techniques
Timing-Driven Placement
This technique positions cells along paths that are critical for timing, helping to reduce delays.
Congestion-Driven Placement
Cells are arranged to minimize track usage and reduce congestion in the design.
High Fanout Net Synthesis (HFNS)
For nets with high fanout, such as reset or scan enable signals, the tool optimizes connections by adding buffers. This ensures that the load capacitance is manageable and signal integrity is maintained.
Scan Chain Reordering
During the Design for Test (DFT) phase, flip-flops are organized into scan chains for testing purposes. The tool rearranges these chains to improve routing, connecting nearby flip-flops without compromising their functionality.
Checks After Placement in VLSI
Once the placement is complete, the following checks are performed:
- Legalization Verification: Ensure all placements comply with established constraints.
- Power Connections: Confirm that all cells are properly connected to power and ground.
- Congestion and Density Maps: Review maps to ensure all metrics fall within acceptable limits.
- Timing Quality Assessment: Evaluate the design for violations in timing (WNS and TNS).
- Design Utilization Evaluation: Assess the total utilization of the design post-placement.
- Congestion Levels: Ensure congestion levels are manageable to prevent future routing issues.
Conclusion
The placement in VLSI design is complex yet crucial for ensuring high performance and efficiency. By following the outlined steps and techniques, designers can optimize the arrangement of standard cells, addressing timing, power, and congestion concerns. This structured approach leads to a robust design ready for further stages like clock tree synthesis and routing, ultimately contributing to the overall success of the VLSI chip.
