Focuses on PCIe interrupts, error detection, error handling, and layer-wise error classification.
1. PCIe Interrupts Overview
PCIe supports modern interrupt mechanisms to notify the CPU of events:
| Interrupt Type | Description |
|---|---|
| INTx | Legacy pin-based interrupts (emulated in PCIe) |
| MSI | Message Signaled Interrupts; sent as TLPs |
| MSI-X | Extended MSI; multiple vectors for different events |
PCIe prefers MSI/MSI-X because INTx is slow and limited.
2. INTx Emulation
- PCIe endpoints emulate legacy PCI INTx via messages
- INTx signals converted into TLP messages to CPU
- Supports backward compatibility with older drivers
ASCII Example:
Endpoint INTx Trigger -> PCIe TLP -> Root Complex -> CPU
3. MSI & MSI-X
- MSI: Single interrupt vector delivered as TLP
- MSI-X: Supports multiple vectors, improving interrupt granularity
- Each vector can be routed to different CPU cores for parallelism
ASCII MSI-X Example:
[EP] -> TLP Vector 0 -> CPU Core 0
[EP] -> TLP Vector 1 -> CPU Core 1
[EP] -> TLP Vector 2 -> CPU Core 2
4. Error Detection in PCIe
PCIe supports multi-layer error detection:
| Layer | Mechanism |
|---|---|
| Transaction Layer | TLP CRC, sequence number checking |
| Data Link Layer | DLLP CRC, replay buffers, ACK/NAK |
| Physical Layer | 1b/1b or 128b/130b encoding, FEC (Gen6), alignment errors |
ASCII Example:
[TLP sent] -> PHY -> DLL -> CRC OK? -> TL
If error: NAK + Replay
5. Error Handling Mechanisms
- Replay: Retransmit corrupted TLPs (DLL Layer)
- Corrected Errors: FEC or scrambler corrections (PHY)
- Uncorrectable Errors: Reported to CPU via AER (Advanced Error Reporting)
- Device Recovery: Optional link retraining or hot reset
6. Layer-wise PCIe Error Classification
| Layer | Error Type | Severity | Handling |
|---|---|---|---|
| Transaction | Bad TLP Header / Payload | Recoverable | Replay / NAK |
| Data Link | CRC mismatch, sequence error | Recoverable | Replay / DLCMSM |
| Physical | Alignment loss, encoding error | Recoverable / Fatal | FEC / Hot Reset |
| System | Configuration error | Fatal | AER / System Reset |
Layered error handling ensures robustness even at high speeds.
7. Advanced Error Reporting (AER)
- PCIe devices can report errors to software
- Supports correctable, uncorrectable non-fatal, and fatal errors
- Enables diagnostics, recovery, and logging
ASCII AER Flow
[TLP Error Detected] -> Device -> AER TLP -> CPU -> OS logs
8. Summary – PCIe Interrupts & Error Handling
Responsibilities:
- Interrupt mechanisms: INTx, MSI, MSI-X
- Layered error detection (TL/DLL/PHY)
- Replay, FEC, hot reset, and device recovery
- Layer-wise error classification
- Advanced error reporting to software for diagnostics
