Focusing on the Physical Layer (Gen1–Gen4), encoding, framing, link initialization, and special symbols.
1. Physical Layer Overview
The Physical Layer (PHY) is responsible for:
- Transmitting and receiving serial data across lanes
- Converting TLPs/DLLPs into electrical signals
- Encoding/decoding for signal integrity
- Handling link initialization, equalization, and training
ASCII Layer Diagram
+--------------------+
| Transaction Layer | <- TLPs
+--------------------+
| Data Link Layer | <- DLLPs
+--------------------+
| Physical Layer | <- Electrical signals over lanes
+--------------------+
Key Functions:
- Lane serialization/deserialization
- Signal integrity (scrambling, equalization)
- Framing TLPs/DLLPs
- Generating and processing ordered sets
- Link speed negotiation and recovery
2. PCIe Physical Layer Generations
| Gen | Year | Lane Speed | Encoding | Max x16 Bandwidth |
|---|---|---|---|---|
| Gen1 | 2003 | 2.5 GT/s | 8b/10b | 4 GB/s |
| Gen2 | 2007 | 5 GT/s | 8b/10b | 8 GB/s |
| Gen3 | 2010 | 8 GT/s | 128b/130b | 16 GB/s |
| Gen4 | 2017 | 16 GT/s | 128b/130b | 32 GB/s |
Gen1/2 use 8b/10b encoding
Gen3/4 use 128b/130b encoding for efficiency
3. Encoding & Scrambling
3.1 8b/10b Encoding (Gen1/Gen2)
- Converts 8-bit data to 10-bit symbols
- Ensures DC balance and enough transitions for clock recovery
- Prevents long sequences of 0s or 1s
ASCII Example
Data: 10101100 -> 10-bit encoded: 1010110010
- Used for special symbols like Start-of-Frame or Ordered Sets
3.2 128b/130b Encoding (Gen3/Gen4)
- Groups 128 bits of payload + 2-bit header → 130-bit symbol
- Reduces overhead vs 8b/10b
- Supports higher bandwidth
3.3 Scrambling
- Randomizes the bit stream to reduce electromagnetic interference (EMI)
- Applied per lane
- Ensures signal integrity across long traces
4. Link Initialization and Training (LTSSM)
PCIe links go through Link Training and Status State Machine (LTSSM):
ASCII LTSSM Simplified States
Detect
|
V
Polling
|
V
Configuration
|
V
L0 (Active)
|
L0s/L1 (Low power)
- Detect: PHY detects connection
- Polling: Negotiates speed and lane width
- Configuration: Assigns device IDs, completes training
- L0: Active link
- L0s/L1: Low-power states
5. Special Symbols & Ordered Sets
PCIe uses special sequences for link management:
| Symbol / Ordered Set | Purpose |
|---|---|
| TS1 | Lane initialization and training |
| TS2 | Further lane equalization |
| EIOS (End-of-Initialization Ordered Set) | Marks end of training phase |
| EIEOS (End-of-Initialization EIOS) | Confirms link is ready |
ASCII Example: Ordered Set Flow
[TS1] -> [TS2] -> [EIOS] -> [EIEOS] -> Link Active
Ordered sets are critical for reliable Gen3/Gen4 operation.
6. Start-of-Data Stream (OS) and Framing
- Framing tokens indicate TLP boundaries
- OS sequences are inserted to align the physical stream with DLL and Transaction layers
- Ensures TLP/DLLP are correctly reconstructed at the receiver
7. Low-Power States
PCIe PHY supports link power management:
| State | Description |
|---|---|
| L0 | Fully active |
| L0s | Low power with partial activity |
| L1 | Deeper low power (clock stopped) |
| Disabled | Link inactive, device idle |
| Loopback | PHY loops back data internally (testing) |
| Hot Reset | Force reset for recovery |
✅ Low-power states are used to save energy without affecting performance.
8. Clock Tolerance Compensation & Equalization
- PCIe uses Decision Feedback Equalization (DFE) and other techniques to compensate for signal degradation
- Receiver adapts to incoming signals dynamically
- Critical for high-speed links (Gen3/Gen4/Gen5/Gen6)
9. Summary – Physical Layer
Responsibilities:
- Serial data transmission and reception
- Encoding (8b/10b or 128b/130b)
- Framing and scrambling
- Link initialization and training (LTSSM)
- Ordered sets (TS1, TS2, EIOS, EIEOS)
- Low-power states and equalization
