PCIe device types, configuration space, headers, and the transaction layer basics.
1. PCIe Device Types
PCIe devices are organized into specific roles:
| Device Type | Description |
|---|---|
| Root Complex (RC) | Connects CPU to PCIe hierarchy; initiates transactions |
| Endpoint (EP) | Actual devices like GPU, SSD, NIC, FPGA |
| Switch | Extends connectivity to multiple endpoints |
| Bridge | Connects PCIe hierarchy to older buses (PCI/PCI-X) |
| Root Port | Port on RC connecting to downstream devices |
ASCII Topology Example
CPU / Root Complex
|
Root Port
|
Switch
/ | \
EP1 EP2 EP3
(GPU) (SSD) (NIC)
Each device communicates via dedicated point-to-point links.
2. PCIe Configuration Space
Every PCIe device has a configuration space to manage:
- Device identity
- Resource allocation
- Power management
- Capabilities
Key Components:
| Field | Purpose |
|---|---|
| Vendor ID / Device ID | Identify manufacturer & device |
| Status / Command | Control device functionality |
| BAR (Base Address Registers) | Map device memory / IO space |
| Type 0 / Type 1 headers | Type 0 for endpoints, Type 1 for bridges |
| Capability Registers | Extended features like MSI, MSI-X, Power Management |
| L0s / L1 Updates | Low-power link states |
2.1 Type 0 vs Type 1 Headers
| Header Type | Use Case |
|---|---|
| Type 0 | Endpoint devices |
| Type 1 | Bridges between PCIe hierarchies (like switches) |
Key Differences:
- Type 0 headers define BARs for memory and IO mapping
- Type 1 headers manage downstream device enumeration and address translation
3. Base Address Registers (BARs)
BARs define where device memory or IO appears in system address space.
- Memory-mapped BARs: map device registers to system memory
- IO BARs: map device registers to IO space
Example:
BAR0: 0xD0000000 – 0xD0000FFF (Memory space)
BAR1: 0x0000C000 – 0x0000C0FF (IO space)
BARs allow the CPU to read/write device registers directly.
4. Capability Registers
Used to extend PCIe features:
| Capability | Description |
|---|---|
| MSI / MSI-X | Interrupts without dedicated pins |
| Power Management | ASPM, L0s, L1 support |
| Advanced Features | Address Translation Services (ATS), TPH, PASID |
5. Transaction Layer (TL)
The Transaction Layer is responsible for creating, routing, and processing TLPs (Transaction Layer Packets).
5.1 TLP Basics
| Component | Description |
|---|---|
| Header | Routing, type, addresses |
| Payload | Actual data being transferred |
| CRC | Ensures integrity of packet |
TLP Types:
- Memory Read / Write – Access system or device memory
- IO Read / Write – Access IO registers
- Configuration Read / Write – Access device configuration space
- Message – Interrupts, notifications, and other messages
ASCII TLP Structure
+----------------+----------------+-------------+
| Header | Payload | CRC |
+----------------+----------------+-------------+
5.2 Transaction Layer Routing
PCIe uses multiple routing methods:
| Routing Type | Description |
|---|---|
| Address-based | Uses destination address for TLP routing |
| ID-based | Uses requester ID or device ID |
| Implicit | System-defined special routing (e.g., broadcasts) |
Root Complex and switches handle TLP forwarding according to routing rules.
5.3 Transaction Processing Hints (TPH)
- Hints allow endpoints to suggest how completions should be handled
- Reduces latency and improves memory efficiency
5.4 Prefix & PASID
- TLP Prefix: Additional header before main TLP for special transactions
- PASID (Process Address Space ID): Supports virtualization by tracking multiple process address spaces
5.5 Virtual Channel (VC) Management & QoS
PCIe supports multiple virtual channels:
- Separate logical lanes for different traffic types
- Prioritize critical data (like interrupts) over bulk data
- Enhances Quality of Service (QoS)
