Focuses on PCIe Gen5/Gen6 Physical Layer enhancements, Flit Mode, 1b/1b encoding, FEC, buffers, and handshake phases.
1. Gen5 & Gen6 Physical Layer Enhancements
| Feature | Description |
|---|---|
| Speed | Gen5 = 32 GT/s, Gen6 = 64 GT/s |
| Encoding | Gen6: 1b/1b encoding with scrambling; FEC for error correction |
| Equalization Enhancements | Advanced DFE and CTLE for high-speed links |
| Clock Tolerance Compensation | Ensures lane-to-lane synchronization at extreme speeds |
| Retimer Support | Optional for long traces to maintain signal integrity |
ASCII Example – Gen6 Lane
[TX] -> 1b/1b Encode -> Scramble -> Trace -> FEC -> [RX Decode]
2. Flit Mode Overview
- Flit (Flow Control Unit) mode is used in Gen6 links
- Breaks TLP into smaller units called flits for faster error detection and recovery
- Types of Flits: Idle, NOP, Payload
- Includes implicit and explicit sequence numbers
ASCII Flit Structure
[Flit Header][Flit Payload][Flit Trailer]
3. 1b/1b Encoding & Scrambling
- Each data bit transmitted is mapped to a single physical bit
- Reduces overhead compared to 128b/130b
- Scrambling ensures DC balance and reduces EMI
ASCII Example
Data Bit: 1 -> Transmitted as 1 (Scrambled)
Data Bit: 0 -> Transmitted as 0 (Scrambled)
4. Transmit & Receive Buffers
- Transmit buffer: Holds flits before sending; supports replay in case of NAK
- Receive buffer: Holds incoming flits, reorders and reconstructs TLPs
- Flit Replay Mechanism: Retransmit flits on error detection
ASCII Buffer Example
TX Buffer: [Flit1][Flit2][Flit3]
RX Buffer: [Flit1][Flit2 (corrupt)] -> NAK -> TX Replay Flit2
5. Handshake Phases in Flit Mode
| Phase | Purpose |
|---|---|
| IDLE Flit Handshake | Initialize link, maintain idle state |
| Sequence Number Handshake | Synchronize sequence numbers between TX/RX |
| Normal Flit Exchange | Transmit payload flits with ACK/NAK handling |
| Replay Scheduling | Schedule retransmission of corrupted flits |
ASCII Handshake Flow
TX: Flit1 -> RX: ACK
TX: Flit2 -> RX: NAK -> TX Replay Flit2
TX: Flit3 -> RX: ACK
6. FEC & Its Role in Physical Layer
- Forward Error Correction (FEC) reduces retransmissions by correcting small errors at RX
- Combined with sequence numbers, ensures high link reliability at 64 GT/s
- Works alongside scrambling, equalization, and replay mechanisms
7. Flit Sequencer Rules
- Transmitter and receiver maintain separate sequence numbers
- Ensures TLPs reconstructed in correct order
- Handles implicit vs explicit sequence numbering
- Critical for multi-lane links to maintain alignment
ASCII Flit Sequence
TX Seq#: 1,2,3
RX Seq#: 1 -> OK, 2 -> NAK -> Replay, 3 -> OK
8. Ordered Set Updates
- TS0, TS1, TS2, EIOS, EIEOS for link initialization and training
- Half scrambling updates to reduce EMI
- Equalization enhancements in Gen6 for long trace links
- Clock tolerance compensation ensures stable operation at extreme speeds
9. Summary – Gen5/Gen6 Physical Layer & Flit Mode
Responsibilities:
- Support high-speed 32–64 GT/s links
- Encode data via 1b/1b with scrambling
- Use Flit Mode for faster error detection and TLP reconstruction
- Maintain TX/RX buffers, sequence numbers, replay mechanism
- Perform FEC, equalization, and clock tolerance compensation
- Use Ordered Sets (TS0, TS1, TS2, EIOS/EIEOS) for link training
