PCIe Protocol – Part 12 - logicmadness.com

Focuses on PCIe Physical Layer (Gen1–Gen4), encoding, framing, special symbols, and link training.

Table of Contents

1. PCIe Physical Layer Overview

The Physical Layer (PHY) converts digital TLP/DLLP data into electrical signals for transmission over PCIe lanes:

Supports Gen1 to Gen4 speeds
Performs encoding, scrambling, framing, and equalization
Manages link initialization, recovery, and speed change

ASCII PHY Layer Diagram

+--------------------+
| Transaction Layer  |
+--------------------+
| Data Link Layer    |
+--------------------+
| Physical Layer     |
| - TX / RX lanes    |
| - Encoding / Framing |
| - Equalization      |
+--------------------+

2. Gen1 & Gen2 Encoding

Speed: Gen1 = 2.5 GT/s, Gen2 = 5 GT/s
Encoding: 8b/10b
- Maps 8-bit data to 10-bit symbols
- Ensures DC balance and enough transitions for clock recovery
Framing & Special Symbols:
- SKP: Skip symbol to align lanes
- COM: Start-of-packet or link control
- IDLE: No data, keeps link alive

ASCII 8b/10b Example

Data byte 0xAB -> 10-bit symbol 0b1010110010

3. Gen3 & Gen4 Encoding

Speed: Gen3 = 8 GT/s, Gen4 = 16 GT/s
Encoding: 128b/130b
- 128-bit data + 2-bit sync header
- Reduced overhead compared to 8b/10b
Ordered Sets: TS1, TS2, EIOS, EIEOS, FTS, SKPOS
- TS1/TS2: Link training and initialization
- EIOS / EIEOS: End-of-start-of-stream markers
- FTS / SKPOS: Framing and symbol placement

ASCII 128b/130b Stream Example

[Sync Header][128-bit Payload] -> [Ordered Set TS1/TS2] -> Link

4. Link Initialization & Training

Managed via LTSSM (Link Training & Status State Machine)
States:

LTSSM State	Description
Detect	Physical connection detected
Polling	Verify link width & speed
Configuration	Exchange link capabilities
L0 / L0s	Active data transmission
Recovery	Error recovery and retransmission
Loopback	Test mode for PHY
Hot Reset	Reset link without power cycling
Disabled	Link inactive

ASCII LTSSM Flow

Detect -> Polling -> Configuration -> L0
                         |
                         v
                     Recovery / Loopback

5. Link Parameters & Recovery

Link width negotiation (x1, x4, x8, x16)
Speed negotiation (Gen1–Gen4)
Recovery states handle symbol misalignment, CRC errors, or lane skew

6. Equalization

Receiver Equalization: Compensates for trace loss, reflections, and crosstalk
Transmitter Preshoot / De-emphasis: Reduces high-frequency signal distortion
Essential for Gen3+ links to maintain signal integrity at high speeds

ASCII Equalization Concept

TX: Data -> Preshoot / De-emphasis -> Trace
RX: Signal -> DFE / CTLE -> Decode -> TLP

7. Low Power States

Managed at PHY and Link layer
Includes L0s, L1, and partial lane shutdown
Clock Tolerance Compensation: Adjusts for clock variation between devices

8. Summary – PCIe Physical Layer (Gen1–Gen4)

Responsibilities:

Encode/decode data (8b/10b for Gen1/2, 128b/130b for Gen3/4)
Frame TLPs and DLLPs using ordered sets
Perform link training, width/speed negotiation, and recovery
Equalize signals for high-speed data integrity
Handle low-power states and clock tolerance