In this article, we will explore the key inputs required to begin the physical design process. In our previous article, we covered the physical design flow and sanity checks before floor planning. Inputs for physical design can be classified into two categories: mandatory and optional inputs. These are crucial to ensure the design progresses smoothly. Below, we categorize and explain these inputs in detail.
Inputs for Physical Design: Mandatory vs Optional
The required inputs for physical design can be broadly divided into mandatory and optional categories. Figure 1 shows a list of these inputs and their classification.
Inputs Required for Physical Design
1. Design-Related Input Files
The primary input files are design-related files, which consist of the Gate Level Netlist and Design Constraint Files. These files come from the synthesis team and contain important information necessary for physical design. Let’s dive deeper into these files:
Gate Level Netlist
The gate-level netlist is the result of synthesis. The synthesis team converts the RTL (Register Transfer Level) code into a gate-level netlist using standard cell libraries and constraints. This netlist contains all instances of the design and their interconnections. It is essential for the design process as it helps to map the design at the gate level.
Constraint File
Also known as the SDC (Synopsys Design Constraints) file, the constraint file is critical for setting timing and design rules. It contains the following:
- Units: Time, Capacitance, Resistance, Voltage, Current, Power
- System Interface: Driving cell, Load
- Design Rule Constraints: Max fanout, max transition
- Timing Constraints: Clock definitions, clock latency, clock uncertainty, input/output delay
- Timing Exceptions: Multi-cycle and false paths
For a more detailed explanation of SDC files, please refer to other related resources.
2. Standard Cell Libraries
Input files related to standard cell libraries are also vital for the physical design process. These files are provided by the standard cell library vendor and fall into three categories:
Logical Libraries
The logical library, also known as the timing library or power library, contains key data about standard cells, including:
- Timing Details: Delay, transitions
- Setup and Hold Time: Timing characteristics
- Functionality Details: Cell functionality
- Area: Size of standard cells
- Pins: Direction, capacitance, location
- Leakage Power: Power consumption of standard cells
The .lib file format is typically used for Cadence tools, and Synopsys tools use the .db format. These files are created through standard cell library characterization by the vendor.
Physical Libraries
The physical library describes the layout of the standard cells and macros. This includes:
- Size: Height and width of cells
- Symmetry: Symmetry of the cell
- Pin Information: Name, direction, shape, layer, and location of pins
Physical libraries are typically in .lef format for Cadence tools and .CELL and .FRAM formats for Synopsys tools. These files are also provided by the standard cell library vendor.
Technology File
The Technology File is essential for defining the manufacturing process and rules for physical design. It contains detailed information about the metal layers, vias, and design rules, including:
- Manufacturing Grid
- Layers: Poly, Contact, Metal1, Via2
- Metal Direction: Types and directions of metals
- Pitch, Width, Spacing
- Resistance: Per square unit
The .techlef format is used by Cadence tools, while Synopsys tools use the .tf format.
RC Coefficient File
The RC Coefficient File is used for RC extraction and estimation. It helps to analyze the resistance and capacitance of interconnects in the design. This is crucial for accurate physical design and verification.
MMMC View File
The Multi-Mode Multi-Corner (MMMC) View File is used to generate different analysis views based on varying delay corners and constraints. The delay corners depend on the library sets and RC corners, which are based on voltage and temperature values.
3. Optional Input Files
Some input files are required primarily for block-level PnR (Place and Route) implementation. These files help refine the design at the block level. These optional inputs include:
Block Partition
For block-level PnR, you need a defined core area for each block. The block’s shape can be rectangular or complex rectilinear. This partitioning defines the size and shape of the blocks within the chip.
Pin Definition (Pin Def)
Pin locations for blocks are predefined by the full-chip owner. For block-level PnR, these pin locations must match with the other blocks. Typically, pin locations are given in a .def file. In case of pin placement issues, the block owner can request modifications.
Power Plan Script
For block-level PnR, the power plan must be consistent with the full-chip power plan. A power plan script (usually in .tcl format) is used to define the power rules and configuration for the block.
Power Intent File (UPF | CPF)
The Power Intent File defines how power is routed to individual blocks, and when each block should be powered on or shut down. The two common formats for power intent files are:
- Unified Power Format (UPF): Used by tools like Synopsys
- Common Power Format (CPF): Used by Cadence tools
This file is particularly important for designs with multiple voltage domains.
Switching Activity Files (VCD | SAIF)
The Switching Activity Files (either VCD or SAIF) are used for dynamic IR analysis. This analysis helps to detect dynamic power drops in the chip based on switching activities. The switching activity data is crucial for power estimation and ensuring the chip’s performance meets expectations.
Summary of Inputs for Physical Design
| Input Category | Mandatory | Optional |
|---|---|---|
| Design Files | Gate Level Netlist, Constraint File | – |
| Standard Cell Libraries | Logical Libraries, Physical Libraries, Technology File | – |
| RC Coefficient File | Yes | – |
| MMMC View File | Yes | – |
| Block-Level Files | – | Block Partition, Pin Def, Power Plan Script, Power Intent File, Switching Activity Files |
These inputs form the foundation for physical design. Understanding these files and their significance will help you efficiently execute the design process.
Example Code for Physical Design Inputs
# Define input files and parameters
gate_level_netlist = "path_to_netlist/file"
constraint_file = "path_to_constraint/file"
technology_file = "path_to_technology/file"
# Example of reading the constraint file
def read_constraint_file(file_path):
with open(file_path, 'r') as file:
constraints = file.readlines()
return constraints
# Function to check if all required inputs are available
def check_inputs(inputs):
for input_file in inputs:
if not os.path.exists(input_file):
print(f"Missing input file: {input_file}")
return False
return True
# List of all input files for physical design
input_files = [gate_level_netlist, constraint_file, technology_file]
# Check if all required inputs are available
if check_inputs(input_files):
print("All required inputs are available.")
else:
print("Some input files are missing.")
This code ensures that all required input files are available and ready for processing. It checks for missing files and prompts the user accordingly.
