VLSI (Very Large Scale Integration) technology is the process of designing complex chips and Systems on Chips (SoCs) by packing billions of transistors into a single chip. These chips are crucial in many industries, including data centers, telecommunications, automotive, defense, consumer electronics, and industrial automation. Designing these tiny chips, with intricate circuits built using billions of transistors, is a challenging and multi-step process. In VLSI, chips, especially ASICs (Application-Specific Integrated Circuits), can be designed using two main approaches: Full-Custom and Semi-Custom design methodologies.

Full-Custom Design Methodologies

In Full-Custom Design, every aspect of the chip is tailored from the ground up. Engineers design all the logic components starting at the transistor level. This involves customizing the transistors’ size (length and width) and arranging the floor plan and routing layout. This level of customization ensures optimal performance in terms of power consumption, chip area, and signal delays.

However, because no pre-designed standard cells are used, Full-Custom design is complex, time-consuming, and costly. Despite these challenges, it is ideal for high-volume production where performance optimization is critical. SPICE modeling is often used for characterization in this design flow.

Semi-Custom Design Methodologies

In contrast, Semi-Custom Design uses pre-designed, pre-tested, and pre-characterized standard cells. Engineers combine these standard cells with additional components that may not be available in the standard library. This method significantly reduces design time since many elements are already designed and verified. However, the design may not be fully optimized for parameters like power, area, and propagation delay.

Semi-Custom design is useful when speed to market is a priority, and it’s often used for smaller production runs or prototypes.

The Full-Custom Design Flow

Now, let’s take a closer look at the Full-Custom design flow, which involves converting a RTL (Register Transfer Level) netlist into a manufacturable layout (GDS-II file). This is a multi-step process that ensures the chip is ready for production.

1. Partitioning

The first step in physical design is partitioning. Here, the complex circuit is divided into smaller subsystems or blocks. This makes the design more manageable by minimizing the interconnections between these blocks.

2. Floor Planning

Next, engineers decide the rough placement of each block on the silicon chip. They also determine the shape and size of each block and the locations of pin connections. Proper floor planning ensures that blocks can be interconnected efficiently in later steps.

3. Placement

Placement determines the exact location of each subsystem on the chip. Engineers focus on leaving enough space between blocks for power supply lines (Vdd and Ground) and interconnect wires. Adequate spacing ensures the design isn’t cluttered and that the chip can function as planned.

4. Clock Tree Synthesis (CTS)

Once placement is complete, the chip will contain numerous flip-flops spread across the design. The challenge is ensuring that the clock signal reaches all these flip-flops with minimal delay differences, known as clock skew.

Clock Tree Synthesis (CTS) ensures that the clock signal reaches all flip-flops at nearly the same time, minimizing skew. Engineers choose a tree topology structure to balance the wire lengths in the clock distribution network, ensuring uniformity in clock signal delivery.

5. Routing

Routing is the process of connecting different blocks using interconnect wires. Engineers aim to minimize the length of these wires to meet timing requirements while keeping the chip area as small as possible. Proper routing also avoids congestion, reducing the chance of manufacturing defects.

6. Static Timing Analysis (STA)

After routing, Static Timing Analysis is performed on the final netlist to verify that the design meets timing requirements, such as maximum operating frequency. STA ensures that the chip will function at the desired speed without violating setup or hold time constraints. If there are timing violations, adjustments to placement and routing may be required.

7. Post-Timing Checks

Once the timing is validated, the physical layout is extracted. This layout will be used during the fabrication process to create the masks used in photolithography.

8. Design Rule Check (DRC)

The next step is the Design Rule Check (DRC). This ensures the layout follows the design rules set by the foundry, ensuring manufacturability and minimizing the risk of fabrication errors.

9. Layout vs. Schematic (LVS)

Finally, Layout vs. Schematic (LVS) checking is done to confirm that the design’s functionality has not been altered during the physical design process. LVS compares the layout with the schematic to ensure that all devices and connections match correctly.

Summary of the Full-Custom Design Flow

Step	Description
Partitioning	Break the design into smaller, manageable subsystems.
Floor Planning	Decide the placement and pin locations of each block.
Placement	Position the subsystems on the chip while ensuring enough space for wiring.
Clock Tree Synthesis (CTS)	Ensure the clock signal reaches all flip-flops with minimal skew.
Routing	Connect the blocks with minimal wire length while avoiding congestion.
Static Timing Analysis (STA)	Validate that the design meets timing requirements.
Post-Timing Checks	Extract the physical layout for fabrication.
Design Rule Check (DRC)	Ensure the layout follows foundry design rules for manufacturability.
Layout vs. Schematic (LVS)	Verify that the layout matches the schematic and performs correctly.

Final Steps

Once the design flow, including floor planning, placement, CTS, routing, and verification (DRC and LVS), is completed, the final GDS-II file is sent to the foundry. The foundry then uses this file to fabricate the actual silicon chips.

Growing Demand for VLSI Engineers | Full Custom and Semi Custom Design Methodologies

As the demand for integrated circuits (ICs) continues to rise, the need for skilled VLSI engineers is growing rapidly. Professionals specializing in physical design and verification play a crucial role in bringing complex chips to life. If you’re interested in pursuing a career in this field, a VLSI Physical Design course with 100% placement assistance could be a great step forward.