A FloorPlanning in VLSI is the arrangement of components in a systematic way. Think of it like planning a house: before construction, you need a blueprint. Similarly, in physical design (PD), a good floorplan is essential. It significantly impacts your design’s quality, ensuring better power, performance, and area (PPA).
FloorPlanning in VLSI involves several tasks: creating the core area, setting the boundaries between the core and input/output (I/O), arranging standard cell rows, placing I/O pins, positioning macros according to guidelines, and adding placement blockages and halos. These steps help optimize space for standard cells, reduce congestion, and prevent issues like IR drop.
Necessity of Floorplanning in VLSI
Floorplanning in VLSI (Very Large Scale Integration) is a critical step in the design process. It involves organizing the layout of a chip to optimize various performance metrics. Here are some key reasons why floorplanning is essential:
- Optimizes Performance
A well-designed floorplan can significantly enhance the performance of the chip by minimizing signal delay and improving overall circuit speed. - Reduces Power Consumption
Efficient FloorPlanning in VLSI helps in reducing power usage by optimizing the placement of components, leading to shorter interconnect lengths and less energy loss. - Maximizes Area Utilization
By effectively organizing the layout, FloorPlanning in VLSI ensures that available chip area is used efficiently. This helps accommodate more functionality within a smaller footprint. - Prevents Congestion
A good floorplan addresses potential congestion areas by strategically placing blocks and routing paths, which helps avoid bottlenecks during the routing phase. - Facilitates Easy Integration of Macros and Standard Cells
FloorPlanning in VLSI allows for the effective placement of both standard cells and larger macro blocks, ensuring that the design integrates smoothly and functions as intended. - Improves Thermal Management
Proper component placement can help distribute heat more evenly across the chip, reducing hotspots and improving reliability. - Supports Design Rule Compliance
FloorPlanning in VLSI ensures that all design rules and constraints are adhered to, which is crucial for manufacturability and yield. - Enhances Testability
An organized layout makes it easier to implement testing features and methodologies, aiding in fault detection and diagnostics. - Enables Better Routing
A well-thought-out floorplan simplifies the routing process, allowing for efficient paths that reduce resistance and improve signal integrity. - Reduces Time-to-Market
Efficient FloorPlanning in VLSI can shorten the overall design cycle by minimizing rework during the layout and routing stages, helping bring products to market faster.
Types of Designs
There are two main design types:
| Design Type | Description |
| Core Limited Design | The die size is limited by the core area, which may result in fewer I/O pads. |
| Pad Limited Design | The die size is limited by the pad area, making the core area dependent on the pad area. |
Starting the FloorPlanning in VLSI
To begin the floorplan process, you need to load specific input files into the Place and Route (PnR) tool. The required files include:
- Netlist (.v)
- Physical Libraries (.lef) – Tech LEF & Standard Cell LEF
- MMMC
- Timing Libraries (.lib)
- RC Coefficient Files
- SDC
- UPF (Unified Power Format) – (Optional)
- Floorplan DEF (Optional)
Note: Load LEF files before LIB files.
Sanity Checks
Before proceeding, it’s vital to ensure all input files are clean and accurate. Conduct sanity checks to verify data consistency among the files. If any issues arise, address them before moving forward.
Sanity Checks to Perform
- Design Checks: Verify the netlist for issues such as:
- Combinational loops
- Floating inputs
- Multi-driven inputs
- Unintended latches
- Tri-state gates
- Empty modules
- Innovus Tool Command: checkDesign -netlist
- Library Checks: Ensure all cells in the netlist match the libraries.
Innovus Tool Command:- checkDesign -physicalLibrary
- checkDesign -timingLibrary
- Timing Checks: Confirm that the SDC file constrains all paths, ensuring timing consistency.
Innovus Tool Command: check_timing
FloorPlanning Control Parameters
Understanding key parameters is essential for effective floorplan implementation.
Core Area
The core area is where all types of cells, including standard cells, macros, and blockages, are placed. The core area calculation is:
Core Size= (Standard Cell Area + Macro Area + Blockage Area​) / Standard Cell Utilization
Aspect Ratio
The aspect ratio is the relationship between the core’s height and width. A square core has an aspect ratio of 1.0. Calculating the aspect ratio is done as follows:
Aspect Ratio = Height of Core Area / Width of Core Area
Routing Tracks
Metal layers consist of horizontal and vertical routing tracks, essential for routing paths. The distance between tracks is known as the pitch.
Utilization
Utilization measures the area occupied by standard cells, macros, and blockages within the core area, expressed as a percentage:
Utilization = ( Standard Cell Area + Macro Area​ ) / Total Core Area × 100%
Manufacturing Grid
The manufacturing grid defines the minimum area manufacturable by the foundry for a given technology node, specified in the technology LEF file (e.g., 0.005).
Standard Cell Site
This refers to the minimum dimensions of a cell within the core area. All cells must conform to these dimensions.
Standard Cell Rows
Standard cell rows are created to place standard cells in the core area. Each row has a fixed height, but widths can vary.
Inverted Row Concept
In the second row of standard cells, the power supply connections are inverted to save area. This method allows for shared connections and efficient space usage.
Macro Guidelines
Macros are large components used in designs. Guidelines for placing macros include:
- Place macros at the core’s periphery.
- Ensure macro pins face the center of the core.
- Avoid placing macros in the center to prevent complex routing.
- Keep a clear area around macros to maintain routing efficiency.
Types of Placement Blockages
There are three types of placement blockages:
| Type | Description |
| Hard Blockage | Prevents placement of any cells in the area. |
| Soft Blockage | Allows only buffers and inverters in the area. |
| Partial Blockage | Allows limited placement of cells based on a percentage. |
Halo: A specific type of hard blockage that moves with the macros.
Types of Floorplans
There are three floorplan techniques:
| Floorplan Type | Description |
| Abutted Floorplan | No spacing between elements (zero channel spacing). |
| Non-Abutted Floorplan | Allows spacing between elements. |
| Mixed Floorplan | A combination of abutted and non-abutted techniques. |
Outputs of FloorPlaning in VLSI
After completing the floorplan, the following outputs are generated:
- Floorplan DEF
- Macro placement information
- Core boundary and area details
- Pin positions
- Placement and routing blockage positions
By following these guidelines, you can create an efficient FloorPlanning in VLSI that optimizes your design for better performance.
