Clock Tree Synthesis (CTS) is a key process in chip design. It connects the clock from the clock port to the clock pins of sequential cells. The goal is to minimize delays and balance the skew, which is the difference in arrival times of the clock signal at various points. To achieve this, designers use clock inverters and buffers. Don’t worry if some terms seem complex; we’ll explain everything by the end of this article.

Why Are Clock Nets Special?

Clock nets are crucial because they distribute the clock signal across the chip. They usually have high fanout, meaning they connect to many points. However, they are treated differently in design. During High Fanout Net Synthesis (HFNS), clock nets must not be modified with routing to prevent issues.

Clock nets consume 30% to 40% of a chip’s power. They are also sensitive to electromagnetic (EM) effects, so routing them requires special attention, including building a clock tree. In addition, inserting clock gating cells helps control dynamic power usage. Depending on the design’s complexity and clock frequency, building a clock tree can be straightforward or challenging. Regardless, a clock tree is essential for every design.

Types of Clock Tree Structures

Different structures help in building clock trees while minimizing insertion delays and balancing skew. Some common structures include:

H-Tree Structure
X-Tree Structure
Geometric Matching Algorithm (GMA)
Pi Tree Structure
Fishbone Structure

Inputs for Clock Tree Synthesis

To perform Clock Tree Synthesis, several inputs are required:

Placement Database: This includes the netlist after placement and the Placement DEF file.
Technology Files: LEF and Tech LEF files.
Library Files: These include timing libraries and QRC tech files.
Timing Constraints: SDC and UPF files (if there are multiple power domains).
CTS Specification File: This file outlines rules for skew, latency targets, and max/min transition targets for clock nets.

Checklist Before Starting Clock Tree Synthesis

Placement should be completed.
Power and ground nets must be pre-routed.
Estimated congestion should be acceptable.
Estimated timing should show acceptable slack (around 0 ns).
There should be no violations in max transition/capacitance.
Logical/physical libraries should include special clock cells (clkBuf or clkInv).

Goals of Clock Tree Synthesis

The main goals of CTS are:

Achieve minimum skew.
Minimize insertion delay.
Ensure no violations in dynamic range (DRV) and timing (setup and hold).
Manage clock latency.

Understanding Key Concepts of Clock Tree Synthesis

Clock Latency

Latency refers to the time it takes for the clock signal to travel from the source to the sequential element’s clock pin. It includes two components:

  • Source Latency: The time from the clock source to the clock definition point.
  • Network Latency: The time from the clock definition point to the clock pin.

This delay arises from the capacitance and resistance in the nets.

Insertion Delay

Insertion delay is the time taken by the clock to reach the sequential element’s clock pin. It is primarily due to the added delays from clock buffers or inverters. After CTS, latency is often termed insertion delay.

Skew

Skew is the difference in arrival times of the clock at different points. In low-frequency designs, skew might not be a big issue. However, in high-frequency designs, even a slight difference can cause significant problems, affecting setup and hold times.

Types of Skew
  1. Positive Skew: Occurs when the capture clock path delay is longer than the launch clock path delay. This can improve setup time but degrade hold time.
  2. Negative Skew: Happens when the capture path is shorter than the launch path, improving hold time but degrading setup time.

Types of Skew Based on Paths

  • Local Skew: Difference in arrival times between flip-flops that communicate.
  • Global Skew: Difference between the maximum and minimum insertion delays across the design.

Useful Skew

Sometimes, designers intentionally create skew to resolve timing violations by adding or removing buffers. This is known as useful skew. However, it is crucial to ensure that changes in one path do not negatively impact timing in another.

Clock Jitter

Clock jitter refers to the variation in clock edge arrivals compared to an ideal clock. This variation can arise from noise and interference. Jitter affects timing, and there are two main types:

  • Deterministic Jitter: Caused by predictable factors like crosstalk.
  • Random Jitter: Arises from unpredictable factors like thermal effects.

NDR (Non-Default Routing) Rules

Certain nets, especially clock nets, need special routing rules to minimize issues like crosstalk and EM effects. NDR rules may include specific widths and spacings to ensure reliability. Examples include:

  • 2s2w: Double spacing and width.
  • 3s3w: Triple spacing and width.

Steps in Clock Tree Synthesis

CTS generally involves four main steps:

Clustering: Initial creation of a DRV-aware clock tree without balancing.
Balancing: Adjusting the design according to skew group constraints.
Routing: Using a routing engine to establish clock tree connections.
Post Conditioning: Cleaning up minor issues after routing.

Clock Tree Synthesis Exceptions

Some cells or paths might need adjustments for optimization. Key exceptions include:

Stop Pin: Indicates where the clock tree should end.
Nonstop Pin: Allows clock tree connections to extend beyond standard stops.
Float Pin: Accounts for insertion delay within sequential elements.
Exclude Pin: Isolates specific pins from clock tree calculations.

Clock Tree Optimization Techniques

To optimize the clock tree, designers use various techniques:

Buffering
Sizing
Cloning
Load splitting
Voltage threshold (Vt) changing
Instance relocation
Useful skew

Outputs of Clock Tree Synthesis

After completing CTS, the outputs include:

  • Updated netlist
  • CTS DEF file
  • Timing reports (setup and hold)
  • Skew and latency reports

Final Checks After Clock Tree Synthesis

It is essential to perform checks for:

  • Insertion delay compliance
  • Skew compliance
  • Routing congestion
  • Placement legality
  • Signal integrity and crosstalk
  • Clock duty cycle
  • Power consumption of the clock tree

Conclusion

Clock Tree Synthesis is a vital part of chip design, ensuring that the clock signal reaches all necessary components with minimal delays and skew. By understanding the concepts and following the structured approach outlined above, designers can effectively create reliable and efficient clock trees

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