Focuses on the Transaction Layer (TLP types, address spaces, headers, framing, VCs, ordering, prefix rules, and QoS) in a beginner-friendly but technically rich way.
Transaction Layer & TLP Deep Dive
1. Role of the Transaction Layer
The Transaction Layer (TL) is the brain of PCIe communication.
It is responsible for:
✔ Creating and decoding TLPs (Transaction Layer Packets)
✔ Addressing, routing, and ordering
✔ Virtual channels & QoS
✔ Handling reads, writes, and completions
✔ TLP prefix support (PASID, ATS, TPH, etc.)
2. Types of Transactions (TLP Types)
| Category | Transaction |
|---|---|
| Posted | Memory Write, Message |
| Non-Posted | Memory Read, I/O Read/Write |
| Completions | Completion with Data (CplD), Completion without Data (Cpl) |
Posted = Fire & Forget
Non-Posted = Must receive completion
Completion = Response to non-posted request
3. Address Spaces
| Address Space | Usage |
|---|---|
| Memory Space | Device memory, MMIO registers |
| I/O Space | Legacy I/O (rare in modern PCIe) |
| Configuration Space | Device discovery & configuration |
| Message Space | Interrupts (MSI/MSI-X), PME, ERR messages |
4. Virtual Channels (VCs) & Traffic Classes (TC)
- PCIe supports up to 8 VCs (VC0–VC7)
- Each VC maps to one or more Traffic Classes (TC0–TC7)
ASCII Mapping:
TC0 -> VC0 (Default, Low Priority)
TC1 -> VC1 (High Priority)
TC2 -> VC2 (Isochronous / Real-time)
Prevents head-of-line blocking
Enables Quality of Service (QoS)
5. TLP Header Fields (Key Fields)
| Field | Purpose |
|---|---|
| Format | Defines header size (3DW/4DW) & data presence |
| Type | Identifies TLP type |
| TC | Priority |
| TD | Digest (CRC) present? |
| EP | Poisoned error |
| Attributes | RO, No Snoop |
| Length | Payload size |
| Requester ID | Who sent it |
| Tag | Identify transaction |
| Address | Memory/I/O address |
| Byte Enable | Valid bytes |
6. TLP Framing
A complete TLP consists of:
+-----------------+
| TLP Header |
+-----------------+
| Optional Prefix |
+-----------------+
| Payload (Data) |
+-----------------+
| ECRC (optional) |
7. TLP Ordering Rules
Default rules:
- Non-Posted before Posted writes
- Read requests must return completions in order
- Completions must preserve Tag ordering
Relaxed Ordering (RO) bit:
- Allows out-of-order transmission for performance
No Snoop:
- Bypasses CPU cache (for DMA, streaming data)
8. TLP Prefix Rules
Prefixes add extra metadata for advanced features:
| Prefix Feature | Purpose |
|---|---|
| PASID | Process ID for virtualization |
| TPH | Completion steering hints |
| ATS | Address translation for IOMMU |
| Steering Tag | Efficient routing inside switches |
Prefix is processed in both Non-Flit and Flit mode.
9. Transaction Flow Example (Memory Read)
Step 1: RC sends Memory Read TLP (Non-Posted)
Step 2: Device receives request
Step 3: Device sends Completion TLP (CplD) with data
Step 4: RC processes data
Ensures reliable, ordered completion.
10. TLP Flow with Virtual Channels (QoS Example)
High Priority Video Stream -> VC1 (fast path)
Low Priority Logging Data -> VC0 (best-effort)
Scheduler ensures VC1 is served first.
11. Putting It All Together (ASCII Summary)
[Transaction Layer]
|
|-- Create TLP (Header + Prefix + Data)
|-- Apply Ordering Rules (RO, No-Snoop, TC)
|-- Assign Virtual Channel (VC0/VC1)
v
[Data Link Layer]
|
|-- Add Seq #, CRC
|-- Reliable delivery (ACK/NAK)
v
[Physical Layer]
|
|-- Encode, transmit, equalize
12. Why the Transaction Layer is CRITICAL
✔ Manages TLP packet structure
✔ Defines transaction types (read/write/completion)
✔ Implements ordering, QoS, routing
✔ Enables virtualization (PASID, ATS, SR-IOV)
✔ Coordinates with Data Link Layer for reliability
✔ Talks directly to device logic and software API
It is the MOST important layer for architects & verification engineers!
