SystemVerilog "extern" for Method Declarations

In SystemVerilog, class definitions can sometimes get very large and complex, especially when multiple functions and tasks are included. This can make it difficult to quickly identify and understand the available functions and variables within the class. One way to simplify this is by using the extern keyword for method declarations. By using SystemVerilog extern, you can separate the method’s declaration from its implementation, which can help to make your code cleaner and more organized.

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What is the `extern` Keyword in SystemVerilog?

The extern keyword in SystemVerilog is used to declare a method (function or task) without providing its implementation inside the class body. The actual implementation of the method is provided outside the class body, making the code more modular and easier to manage.

Example of Using `extern` in SystemVerilog

Let’s walk through an example to see how the extern qualifier is used:

class ABC;

  // Declare a function with extern keyword
  extern function void display();

endclass

// Outside the class body, we provide the function implementation
function void ABC::display();

   // Display a simple message
   $display ("Hello world");

endfunction

How Does This Work?

Class Declaration: The ABC class contains a method called display() that is declared using the extern keyword.
Function Definition: After the class declaration, the display() function is defined outside of the class body. This is where the actual logic (in this case, printing “Hello world”) is implemented.
Calling the Function: In a testbench (or module), an object of the ABC class is created, and the display() method is called.

Full Example in a Testbench

Below is a complete example showing how to declare the class, define the function, and use it in a testbench module.

module tb;

  // Create an object of class ABC
  initial begin
    ABC abc = new();
    abc.display();  // Call the display method
  end

endmodule

Simulation Log

When running the simulation, you will see the following output:

ncsim> run
Hello world
ncsim: *W,RNQUIE: Simulation is complete.

Advantages of Using `extern`

Code Organization: By using extern, the class definition becomes cleaner and shorter. You only need to declare the function inside the class, and you can define it separately.
Reusability: The function implementation can be reused in multiple places if needed, without being tied directly to the class definition.
Improved Readability: Large classes with many functions and tasks can become difficult to read. Using extern helps improve code readability by separating the declaration and definition of methods.

Comparison: Using `extern` vs. Regular Function Declaration

Feature	Regular Function Declaration	Using `extern`
Function Location	Defined inside the class body	Declared inside the class, defined outside
Code Organization	Can lead to large, complex classes	Cleaner, more modular structure
Readability	May become hard to read with many functions	Improves readability and modularity
Implementation Flexibility	Tightly coupled with the class	Allows implementation outside the class body

Conclusion

Using extern in SystemVerilog allows you to separate function declarations from their implementations, making your code more organized and readable. This technique is especially useful when working with large classes or when you need to implement methods in a different file or location. By adopting this practice, you can improve both the maintainability and readability of your SystemVerilog code.

What is the extern Keyword in SystemVerilog?

Example of Using extern in SystemVerilog