SystemVerilog arrays are essential for organizing and handling multiple data elements efficiently. There are two types of arrays in SystemVerilog: packed arrays and unpacked arrays. Understanding their differences and how to use them is crucial for effective coding in SystemVerilog.

What is a SystemVerilog Packed Array?

A packed array in SystemVerilog is an array where the dimensions are declared before the data identifier name. These arrays are stored as contiguous bits in memory, meaning all the elements are stored next to each other without gaps. This makes them ideal for operations that require direct access to all bits.

Example of a Packed Array

bit [7:0] m_data; // A packed array of 8 bits

Packed Array Structure

Packed arrays can include:

• Single bit data types (like bit, logic, reg)
• Enumerated types
• Packed structures or arrays that are recursively defined

A vector refers to a one-dimensional packed array. For example, bit [7:0] m_data is a vector, which represents 8 bits.

A scalar refers to a single-bit data type, like bit m_data, without specifying a range.

Example Code for One-Dimensional Packed Array (Vector)

module tb;
  bit [7:0] m_data; // A 1D packed array (vector)

  initial begin
    m_data = 8'hA2;  // Assign value to vector
    
    // Display each bit of the vector
    for (int i = 0; i < $size(m_data); i++) begin
      $display ("m_data[%0d] = %b", i, m_data[i]);
    end
  end
endmodule

Simulation Output

m_data[0] = 0
m_data[1] = 1
m_data[2] = 0
m_data[3] = 0
m_data[4] = 0
m_data[5] = 1
m_data[6] = 0
m_data[7] = 1

Multi-Dimensional Packed Arrays

SystemVerilog also supports multi-dimensional packed arrays, where you can divide a vector into smaller sub-fields. For example, a 2D packed array is stored as a contiguous block of bits.

Example of 2D Packed Array

module tb;
  bit [3:0][7:0] m_data; // 2D packed array (4 bits wide, 8 bits long)

  initial begin
    m_data = 32'hface_cafe;  // Assign a value to the array

    // Display the array
    $display ("m_data = 0x%0h", m_data);

    // Print each segment of the 2D array
    for (int i = 0; i < $size(m_data); i++) begin
      $display ("m_data[%0d] = %b (0x%0h)", i, m_data[i], m_data[i]);
    end
  end
endmodule

Simulation Output

m_data = 0xfacecafe
m_data[0] = 11111110 (0xfe)
m_data[1] = 11001010 (0xca)
m_data[2] = 11001110 (0xce)
m_data[3] = 11111010 (0xfa)

What is a SystemVerilog Unpacked Array?

An unpacked array in SystemVerilog is an array where the dimensions are declared after the data identifier name. These arrays do not need to be contiguous in memory, meaning they can be scattered across memory locations. Unpacked arrays can store elements of various data types, including arrays, queues, and dynamic arrays.

Example of an Unpacked Array

bit [7:0] array4[2:0];  // Unpacked array with 3 elements

Types of Unpacked Arrays

• Fixed-size arrays
• Dynamic arrays
• Associative arrays
• Queues

Unpacked arrays are often used in situations where flexibility is needed, such as when the size of the array can change during simulation.

Example Code for Unpacked Array

module tb;
  byte stack [8]; // Unpacked array with 8 elements

  initial begin
    // Assign random values to each element
    foreach (stack[i]) begin
      stack[i] = $random;
      $display ("Assign 0x%0h to index %0d", stack[i], i);
    end

    // Print the contents of the array
    $display ("stack = %p", stack);
  end
endmodule

Simulation Output

Assign 0x24 to index 0
Assign 0x81 to index 1
Assign 0x9 to index 2
Assign 0x63 to index 3
Assign 0xd to index 4
Assign 0x8d to index 5
Assign 0x65 to index 6
Assign 0x12 to index 7
stack = '{'h24, 'h81, 'h9, 'h63, 'hd, 'h8d, 'h65, 'h12}

Multi-Dimensional Unpacked Arrays

Unpacked arrays can also be multi-dimensional. This allows for greater flexibility when you need to store more complex data.

Example of a 2D Unpacked Array

module tb;
  byte stack [2][4]; // 2 rows, 4 columns

  initial begin
    // Assign random values to each slot of the array
    foreach (stack[i])
      foreach (stack[i][j]) begin
        stack[i][j] = $random;
        $display ("stack[%0d][%0d] = 0x%0h", i, j, stack[i][j]);
      end

    // Print the contents of the array
    $display ("stack = %p", stack);
  end
endmodule

Simulation Output

stack[0][0] = 0x24
stack[0][1] = 0x81
stack[0][2] = 0x9
stack[0][3] = 0x63
stack[1][0] = 0xd
stack[1][1] = 0x8d
stack[1][2] = 0x65
stack[1][3] = 0x12
stack = '{'{'h24, 'h81, 'h9, 'h63}, '{'hd, 'h8d, 'h65, 'h12}}

Key Differences Between Packed and Unpacked Arrays

Conclusion

SystemVerilog offers two distinct types of arrays: packed and unpacked. Packed arrays store data contiguously, making them ideal for operations requiring direct bit manipulation, while unpacked arrays offer more flexibility, allowing for non-contiguous storage of data. Understanding when and how to use each type of array will improve your SystemVerilog coding practices.