In Verilog, assignment delays can be specified in two ways: inter-assignment delays and intra-assignment delays. These delays help control the timing of when values are assigned to variables in your simulation. The delay can either be placed on the left-hand side (LHS) or the right-hand side (RHS) of the assignment operator.

Inter-assignment Delays

An inter-assignment delay places the delay on the left-hand side (LHS) of the assignment operator. This means the entire assignment operation will be executed after the delay time has passed.

Syntax

#<delay> <LHS> = <RHS>

In this case, the statement will wait for the specified delay before performing the assignment, but the values on the right-hand side (RHS) are evaluated immediately.

Example Code

module tb;
  reg  a, b, c, q;

  initial begin
    // Monitor the values of signals at each time step
    $monitor("[%0t] a=%0b b=%0b c=%0b q=%0b", $time, a, b, c, q);

    // Initialize all signals to 0 at time 0
    a <= 0;
    b <= 0;
    c <= 0;
    q <= 0;

    // Inter-assignment delay: Wait for 5 time units, then assign 1 to 'a' and 'c'
    #5 a <= 1;
    c <= 1;

    // Inter-assignment delay: Wait for 5 more time units, then assign to 'q'
    #5 q <= a & b | c;

    #20;  // Run simulation for 20 more time units
  end
endmodule

Simulation Output

[0] a=0 b=0 c=0 q=0
[5] a=1 b=0 c=1 q=0
[10] a=1 b=0 c=1 q=1

Explanation
In this example, the value of q becomes 1 at time 10 because the RHS of the assignment (a & b | c) is evaluated at that time. Since a is 1, b is 0, and c is 1, the expression evaluates to 1.

Intra-assignment Delays

An intra-assignment delay places the delay on the right-hand side (RHS) of the assignment operator. This means the statement is evaluated immediately, but the actual assignment happens only after the specified delay.

Syntax

<LHS> = #<delay> <RHS>

In this case, the RHS values are evaluated first, and then the result is assigned to the LHS variable after the delay has expired.

Example Code:

module tb;
  reg  a, b, c, q;

  initial begin
    // Monitor the values of signals at each time step
    $monitor("[%0t] a=%0b b=%0b c=%0b q=%0b", $time, a, b, c, q);

    // Initialize all signals to 0 at time 0
    a <= 0;
    b <= 0;
    c <= 0;
    q <= 0;

    // Inter-assignment delay: Wait for 5 time units, then assign 1 to 'a' and 'c'
    #5 a <= 1;
    c <= 1;

    // Intra-assignment delay: First evaluate the RHS, then assign the value to 'q' after 5 time units
    q <= #5 a & b | c;

    #20;  // Run simulation for 20 more time units
  end
endmodule

Simulation Output:

[0] a=0 b=0 c=0 q=0
[5] a=1 b=0 c=1 q=0

Explanation:
In this case, the assignment to q does not appear in the log because of the intra-assignment delay. The RHS (a & b | c) is evaluated immediately, but q gets the value only after the delay of 5 time units. However, the assignment is not detected because the non-blocking assignment does not immediately update the value of a and c during that simulation step.

To fix this, we can switch the assignments for a and c from non-blocking to blocking assignments.

Modified Code:

module tb;
  reg  a, b, c, q;

  initial begin
    // Monitor the values of signals at each time step
    $monitor("[%0t] a=%0b b=%0b c=%0b q=%0b", $time, a, b, c, q);

    // Initialize all signals to 0 at time 0
    a <= 0;
    b <= 0;
    c <= 0;
    q <= 0;

    // Blocking assignments (updated from non-blocking)
    #5 a = 1;
    c = 1;

    // Intra-assignment delay: First evaluate the RHS, then assign to 'q' after 5 time units
    q <= #5 a & b | c;

    #20;  // Run simulation for 20 more time units
  end
endmodule

Simulation Output with Blocking Assignment:

[0] a=0 b=0 c=0 q=0
[5] a=1 b=0 c=1 q=0
[10] a=1 b=0 c=1 q=1

Explanation:
In this version, the values of a and c are updated immediately at time 5 due to the use of blocking assignments (a = 1; c = 1;). Therefore, when q <= #5 a & b | c; is evaluated at time 10, it reflects the updated values of a and c, and q becomes 1.

Comparison Table: Verilog Inter and Intra Assignment Delays

Key Takeaways:

• Inter-assignment delays are used when you want to wait for a specified amount of time before the statement executes, and the RHS is evaluated immediately.
• Intra-assignment delays capture the values on the RHS immediately but only assign them to the LHS after the delay.
• Use blocking assignments when you need immediate updates to signal values in the same time step.